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DTSTAMP:20260402T024533Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T141500
DTEND;TZID=America/Los_Angeles:20250625T143000
UID:dac_DAC 2025_sess136_RESEARCH497@linklings.com
SUMMARY:Cayman: Custom Accelerator Generation with Control Flow and Data A
 ccess Optimization
DESCRIPTION:Youwei Xiao, Fan Cui, Zizhang Luo, Weijie Peng, and Yun (Eric)
  Liang (Peking University)\n\nCustom accelerators enhance System-on-Chips'
  performance through hardware specialization. High-level synthesis (HLS) c
 an automatically synthesize accelerators for given kernels but requires ma
 nual selection and extraction of kernels from applications. This paper pro
 poses Cayman, the first end-to-end framework to synthesize high-performanc
 e custom accelerators with both control flow and data access optimization.
  Cayman automatically selects kernels for hardware acceleration based on a
  hierarchical program representation, which captures kernel candidates wit
 h general control flows. Besides, Cayman optimizes accelerators with speci
 alized processor-accelerator interfaces for data access acceleration. Caym
 an further introduces a novel accelerator merging mechanism to synthesize 
 reusable accelerators. Experiments on various benchmarks demonstrate that 
 Cayman outperforms two state-of-the-art frameworks by 8.0× and 14.4×.\n\nT
 opics: EDA\n\nTracks: EDA5: RTL/Logic Level and High-level Synthesis\n\nSe
 ssion Chairs: Aman Gayasen (Advanced Micro Devices (AMD)) and Christian Pi
 lato (Politecnico di Milano)\n\n
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