BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T140000
DTEND;TZID=America/Los_Angeles:20250625T141500
UID:dac_DAC 2025_sess136_RESEARCH540@linklings.com
SUMMARY:AutoClock: Automated Clock Management for Power-Efficient HLS Desi
 gns on FPGAs
DESCRIPTION:Jiawei Liang (Hong Kong University of Science and Technology (
 HKUST)); Linfeng Du and Xiaofeng Zhou (The Hong Kong University of Science
  and Technology); Zhe Lin (Sun Yat-sen University); Jiang Xu (Hong Kong Un
 iversity of Science and Technology (HKUST), Guangzhou); and Wei Zhang (Hon
 g Kong University of Science and Technology (HKUST))\n\nHigh-level synthes
 is (HLS) tools streamline FPGA design by enabling engineers to implement h
 ardware using C/C++ languages. However, while clock management serves as a
  critical stage in the FPGA EDA flow that affects system-level performance
 , area, and especially power consumption, existing commercial HLS tools la
 ck comprehensive solutions for clock management. Specifically, the diversi
 ty of clock resources creates a vast design space for finding the optimal 
 configuration, and the insufficient analysis of multiple clock domain scen
 arios hinders effective clock-oriented optimizations in HLS. This work int
 roduces AutoClock, an open-source integrated clock management framework th
 at complements AMD Vitis HLS. AutoClock allocates resources for clock gene
 ration, assigns modules to appropriate clock domains, addresses metastabil
 ity and time division multiplexing (TDM) malfunctioning introduced by mult
 i-clock domain architectures, and hierarchically gates the clock of module
 s in a design. Experimental results demonstrate that AutoClock can fully u
 tilize clock resources on FPGAs and help reduce dynamic power consumption 
 by up to 74.38%.\n\nTopics: EDA\n\nTracks: EDA5: RTL/Logic Level and High-
 level Synthesis\n\nSession Chairs: Aman Gayasen (Advanced Micro Devices (A
 MD)) and Christian Pilato (Politecnico di Milano)\n\n
END:VEVENT
END:VCALENDAR