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DTSTAMP:20260402T024534Z
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DTSTART;TZID=America/Los_Angeles:20250623T103000
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UID:dac_DAC 2025_sess139_RESEARCH275@linklings.com
SUMMARY:GLOVA: Global and Local Variation-Aware Analog Circuit Design with
  Risk-Sensitive Reinforcement Learning
DESCRIPTION:Dongjun Kim, Junwoo Park, Chaehyeon Shin, and Jaeheon Jung (Ko
 rea University); Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim,
  Inchul Jeong, and Joohwan Cho (SK hynix); and Jongsun Park (Korea Univers
 ity)\n\nAnalog/mixed-signal circuit design encounters significant challeng
 es due to performance degradation from process, voltage, and temperature (
 PVT) variations. To achieve commercial-grade reliability, iterative manual
  design revisions and extensive statistical simulations are required. Whil
 e several studies have aimed to automate variation-aware analog design to 
 reduce time-to-market, the substantial mismatches in real-world wafers hav
 e not been thoroughly addressed. In this paper, we present GLOVA, an analo
 g circuit sizing framework robust to PVT variations that effectively manag
 es the impact of diverse random mismatches. In the proposed approach, risk
 -sensitive reinforcement learning is leveraged to account for the reliabil
 ity bound affected by PVT variations, and ensemble-based critic is introdu
 ced to achieve sample-efficient learning. For design verification, we also
  propose μ-σ evaluation and simulation reordering method to reduce simulat
 ion costs of identifying failed designs. GLOVA supports verification throu
 gh industrial-level PVT variation evaluation methods, including corner sim
 ulation as well as global and local Monte Carlo simulations.\n\nTopics: ED
 A\n\nTracks: EDA6: Analog CAD, Simulation, Verification and Test\n\nSessio
 n Chairs: Arindam Basu (School of Computer Science and Engineering, Nanyan
 g Technological University) and Markus Olbrich (Leibniz University Hannove
 r)\n\n
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