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DTSTART:19700308T020000
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DTSTAMP:20260402T024534Z
LOCATION:3006\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T113000
DTEND;TZID=America/Los_Angeles:20250625T114500
UID:dac_DAC 2025_sess141_RESEARCH1314@linklings.com
SUMMARY:Comprehensive Placement and Routing Framework with Guaranteed In-C
 ell Routability for Synthesizing Complementary-FET Cells
DESCRIPTION:Zhengzhe Zheng, Yinuo Wu, Keyu Peng, Chao Wang, and Ziran Zhu 
 (Southeast University)\n\nThis paper develops a comprehensive placement an
 d routing framework for synthesizing CFET cells to address scaling issues 
 in advanced nodes. We first develop a BFS-based partitioning technique wit
 h a heuristic quality maintenance strategy to ensure scalability. Then, we
  propose a SMT-based placement method that incorporates partial routing fo
 r minimum-width placement and in-cell routability. Finally, a progressive 
 metal routing method is proposed to address the challenges of routing reso
 urce scarcity. Compared with the state-of-the-art CFET cell generators, ex
 perimental results show that our algorithm achieves the optimal cell width
  for all cells, with 7 out of 30 cells exhibiting smaller widths.\n\nTopic
 s: EDA\n\nTracks: EDA7: Physical Design and Verification\n\nSession Chairs
 : Wuxi Li (Advanced Micro Devices (AMD)) and Bill Swartz (TimberWolf Syste
 ms)\n\n
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