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DTSTAMP:20260402T024534Z
LOCATION:3006\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T110000
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UID:dac_DAC 2025_sess141_RESEARCH1648@linklings.com
SUMMARY:RUPlace: Optimizing Routability via Unified Placement and Routing 
 Formulation
DESCRIPTION:Yifan Chen, Jing Mai, Zuodong Zhang, and Yibo Lin (Peking Univ
 ersity)\n\nPlacement plays a critical role in VLSI physical design, partic
 ularly in optimizing routability. With continuous advancements in semicond
 uctor manufacturing technology, increased integration, and growing design 
 complexity, managing routing congestion during placement has become increa
 singly challenging. Despite the widespread techniques to improve routabili
 ty, these methods often lack theoretical guidance or sever the intrinsic c
 onnection between placement and routing optimization.\nIn this paper, we p
 resent an ADMM-based framework for unified optimization of placement and r
 outing. Leveraging Wasserstein distance and bilevel optimization, our appr
 oach provides a unified framework for congestion optimization by alternate
 ly running global routing and incremental placement. Furthermore, we intro
 duce a simple yet effective model for node inflation-based global placemen
 t, where convex programming is employed to determine the optimal inflation
  ratio.\nExperimental results on a diverse set of open-source industrial b
 enchmarks from CircuitNet and Chipyard demonstrate that our method achieve
 s superior congestion reduction compared to widely used tools such as Open
 ROAD, Xplace 2.0, and DREAMPlace 4.1, while maintaining competitive wirele
 ngth and runtime.\n\nTopics: EDA\n\nTracks: EDA7: Physical Design and Veri
 fication\n\nSession Chairs: Wuxi Li (Advanced Micro Devices (AMD)) and Bil
 l Swartz (TimberWolf Systems)\n\n
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