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DTSTAMP:20260402T024534Z
LOCATION:3006\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T103000
DTEND;TZID=America/Los_Angeles:20250625T104500
UID:dac_DAC 2025_sess141_RESEARCH1870@linklings.com
SUMMARY:DSPlacer: DSP Placement for FPGA-based CNN accelerator
DESCRIPTION:Baohui Xie, Xinrui Zhu, Zhiyuan Lu, Yuan Pu, and Tongkai Wu (T
 he Chinese University of Hong Kong, Shenzhen); Xiaofeng Zou (National Univ
 ersity of Defense Technology); and Bei Yu and Tinghuan Chen (The Chinese U
 niversity of Hong Kong, Shenzhen)\n\nDeploying convolutional neural networ
 ks (CNNs) on Field Programmable Gate Arrays (FPGAs) presents challenges in
  achieving optimal timing closure due to placement's impact on clock frequ
 ency and throughput. We propose DSPlacer, a novel framework for diverse CN
 N accelerator architectures, integrating techniques such as GCN-based DSP 
 identification, DSP graph construction, min-cost-flow assignment, and ILP-
 based cascade legalization. DSPlacer ensures a compact layout while preser
 ving direct datapath connections. Evaluated against AMD Xilinx Vivado 2020
 .2 and AMF-Placer 2.0, DSPlacer improves Worst Negative Slack (WNS) by 32%
  and 65%, demonstrating its effectiveness and scalability.\n\nTopics: EDA\
 n\nTracks: EDA7: Physical Design and Verification\n\nSession Chairs: Wuxi 
 Li (Advanced Micro Devices (AMD)) and Bill Swartz (TimberWolf Systems)\n\n
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