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DTSTAMP:20260402T024533Z
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DTSTART;TZID=America/Los_Angeles:20250625T114500
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UID:dac_DAC 2025_sess141_RESEARCH698@linklings.com
SUMMARY:Synthesis of CFET Cell Library Leveraging Backside Metal Routing
DESCRIPTION:Ting-Xin Lin and Yih-Lang Li (National Yang Ming Chiao Tung Un
 iversity)\n\nAs technology nodes continue to shrink, Complementary FET (CF
 ET) structures, which stack PMOS and NMOS together, have emerged as a prom
 ising candidate for next-generation technology. Due to the reduction in ro
 uting tracks, the insertion of dummy polys to increase routing resources a
 nd the use of M2 during the synthesis of CFET standard cells have become m
 ore inevitable. These two factors make block-level routing significantly m
 ore challenging. To address this, we introduce the methods to utilize the 
 backside (BS) routing resources at the CFET standard cell synthesis stage 
 and efficiently handle CFET transistor folding. To the best of our knowled
 ge, this is the first work to consider BS routing resources at the cell sy
 nthesis stage and efficiently address transistor folding in the CFET stack
 ed structure. In the transistor folding and placement stages, we utilize E
 uler paths to estimate the lower bound of contacted poly pitch (CPP) and a
 pply dynamic programming (DP) to calculate the frontside minimum required 
 tracks (FMRT) of BS-resource-aware placements. The subsequent satisfiabili
 ty modulo theories (SMT) approach determines which tracks the devices occu
 py and completes cell routing. Experimental results show that compared to 
 previous work [11], we achieve reductions of 1%, 45%, and 19% in #CPP, #M2
  tracks, and runtime, respectively.\n\nTopics: EDA\n\nTracks: EDA7: Physic
 al Design and Verification\n\nSession Chairs: Wuxi Li (Advanced Micro Devi
 ces (AMD)) and Bill Swartz (TimberWolf Systems)\n\n
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