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DTSTAMP:20260402T024533Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T144500
DTEND;TZID=America/Los_Angeles:20250624T150000
UID:dac_DAC 2025_sess142_RESEARCH300@linklings.com
SUMMARY:TransRoute: A Novel Hierarchical Transistor-Level Routing Framewor
 k Beyond Standard-Cell Methodology
DESCRIPTION:Chen-Hao Hsu and David Z. Pan (The University of Texas at Aust
 in) and Laurent Perron, Frédéric Didier, Xiaoqing Xu, and Hao Chen (Google
 )\n\nIn advanced technology nodes, benefits from scaling have become limit
 ed in power, performance, and area, necessitating improvements through des
 ign-technology co-optimization (DTCO). However, standard-cell methodology,
  widely used in VLSI design, restricts the potential of DTCO due to its lo
 gic-level abstraction, hindering physical-level optimization. To address t
 his, a transistor-level design approach is needed to break the abstraction
  of standard cells. While large-scale transistor placement has been explor
 ed, efficient routing at the transistor level remains a challenge. This pa
 per introduces a novel transistor-level routing framework with a CP-SAT fo
 rmulation for lower-layer routing, significantly reducing wirelength and d
 esign area compared to traditional standard-cell-based designs.\n\nTopics:
  EDA\n\nTracks: EDA7: Physical Design and Verification\n\nSession Chairs: 
 Michael Kazda (IBM) and Stephan Held (University of Bonn)\n\n
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