BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024507Z
LOCATION:3006\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T133000
DTEND;TZID=America/Los_Angeles:20250625T150000
UID:dac_DAC 2025_sess143@linklings.com
SUMMARY:Navigating 3D, Clock Trees, and Shared Learning
DESCRIPTION:This session highlights advances in 3D IC design and clock tre
 e synthesis (CTS) for improved power and performance. In 3D ICs, 3D-Flow m
 inimizes legalization cell displacement using network flow; DCO-3D uses ma
 chine learning to predict and reduce routing congestion; while GNN-MLS mit
 igates congestion by routing across tiers with metal layer sharing, improv
 ing timing while addressing testability issues. For CTS, we explore approa
 ches using front and back-side metal layers and reinforcement learning bas
 ed "hub" node placement to minimize clock skew, buffering, and wire length
 . Finally, we look into a privacy-protecting, highly accurate federated le
 arning framework to help advance the use of machine learning in EDA.\n\nGN
 N-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Laye
 r Sharing\n\nNative 3D IC design promises commercially viable chips with i
 mproved performance and density. While pseudo-3D flows achieve manufactura
 bility, they fall short of full 3D optimization due to reliance on 2D EDA 
 tools, limiting cross-tier optimization. Metal Layer Sharing (MLS) offers 
 a solution by ena...\n\n\nJiawei Hu (Georgia Institute of Technology), Pru
 ek Vanna-iampikul (Burapha University), Zhen Zhuang and Tsung-Yi Ho (The C
 hinese University of Hong Kong), and Sung Kyu Lim (Georgia Institute of Te
 chnology)\n---------------------\nDCO-3D: Differentiable Congestion Optimi
 zation in 3D ICs\n\nState-of-the-art 3D IC flows fail to consider 3D conge
 stion during earlier stages, leading to excessive use of end-of-flow ECO r
 esources for routability correction that severely degrades full-chip Power
 , Performance, and Area metrics. We present DCO-3D, a Machine Learning bas
 ed routability-aware 3D ...\n\n\nHao-Hsiang Hsiao (Georgia Institute of Te
 chnology), Yi-Chen Lu (Nvidia), Pruek Vanna-iampikul (Burapha University),
  Anthony Agnesina and Rongjian Liang (Nvidia), Yuan-Hsiang Lu (Georgia Ins
 titute of Technology), Haoxing Ren (Nvidia), and Sung Kyu Lim (Georgia Ins
 titute of Technology)\n---------------------\nA Systematic Approach for Mu
 lti-Objective Double-Side Clock Tree Synthesis\n\nAs the scaling of semico
 nductor devices nears its limits, utilizing the back-side space of silicon
  has emerged as a new trend for future integrated circuits. With intense i
 nterest, several works have hacked existing backend tools to explore the p
 otential of synthesizing double-side clock trees via n...\n\n\nXun Jiang a
 nd Haoran Lu (Peking University); Yuxuan Zhao (The Chinese University of H
 ong Kong); Jiarui Wang, Zizheng Guo, and Heng Wu (Peking University); Bei 
 Yu (The Chinese University of Hong Kong); Sung Kyu Lim (Georgia Institute 
 of Technology); and Runsheng Wang, Ru Huang, and Yibo Lin (Peking Universi
 ty)\n---------------------\nFedEDA: Federated Learning Framework for Priva
 cy-Preserving Machine Learning in EDA\n\nIn advanced nodes, the optimizati
 on of Power, Per- formance, and Area (PPA) is becoming increasingly comple
 x, requiring significant resources and time for circuit design and optimiz
 ation using Electronic Design Automation (EDA). As a key approach to overc
 ome these challenges, Machine Learning (ML) t...\n\n\nJoonSeok Kim, Donggy
 u Kim, Seonghyeon Park, and Seokhyeong Kang (Pohang University of Science 
 and Technology (POSTECH))\n---------------------\nTo Tackle Cost-Skew Trad
 eoff: An Adaptive Learning Approach for Hub Node Selection\n\nIn chip desi
 gn, skew is a pivotal factor that significantly influences the overall per
 formance for routing. A major challenge  is how to achieve an appropriate 
 trade-off between the total wire-length cost and skew. Selecting hub nodes
  is an effective method to improve this cost-skew trade-off. In th...\n\n\
 nLin Chen, Guowei Sun, Qiming Huang, and Hu Ding (University of Science an
 d Technology of China)\n---------------------\n3D-Flow: Flow-based Standar
 d Cell Legalization for 3D ICs\n\nThe standard-cell placement legalization
  is a critical step in the physical design. \nThe emerging 3D ICs have bro
 ught challenges to traditional legalizers on efficiency and effectiveness.
 \nIn this work, we present a fast flow-based legalization algorithm, 3D-Fl
 ow, that minimizes cell displacement in ...\n\n\nYuxuan Zhao, Peiyu Liao, 
 and Bei Yu (The Chinese University of Hong Kong)\n\nTopics: EDA\n\nTracks:
  EDA7: Physical Design and Verification\n\nSession Chairs: Igor Markov (Sy
 nopsys) and David Chinnery (Siemens)
END:VEVENT
END:VCALENDAR