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DTSTAMP:20260402T024532Z
LOCATION:3006\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T141500
DTEND;TZID=America/Los_Angeles:20250625T143000
UID:dac_DAC 2025_sess143_RESEARCH1224@linklings.com
SUMMARY:A Systematic Approach for Multi-Objective Double-Side Clock Tree S
 ynthesis
DESCRIPTION:Xun Jiang and Haoran Lu (Peking University); Yuxuan Zhao (The 
 Chinese University of Hong Kong); Jiarui Wang, Zizheng Guo, and Heng Wu (P
 eking University); Bei Yu (The Chinese University of Hong Kong); Sung Kyu 
 Lim (Georgia Institute of Technology); and Runsheng Wang, Ru Huang, and Yi
 bo Lin (Peking University)\n\nAs the scaling of semiconductor devices near
 s its limits, utilizing the back-side space of silicon has emerged as a ne
 w trend for future integrated circuits. With intense interest, several wor
 ks have hacked existing backend tools to explore the potential of synthesi
 zing double-side clock trees via nano Through-Silicon-Vias (nTSVs). Howeve
 r, these works lack a systematic perspective on design resource allocation
  and multi-objective optimization. We propose a systematic methodology to 
 design clock trees with double-side metal layers, including hierarchical c
 lock routing, concurrent buffers and nTSVs insertion, and skew repairing. 
 Compared with the state-of-the-art method, the widely-used open-source too
 l, our algorithm outperforms them in latency, skew, wirelength, and the nu
 mber of buffers and nTSVs.\n\nTopics: EDA\n\nTracks: EDA7: Physical Design
  and Verification\n\nSession Chairs: Igor Markov (Synopsys) and David Chin
 nery (Siemens)\n\n
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