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DTSTAMP:20260402T024532Z
LOCATION:3006\, Level 3
DTSTART;TZID=America/Los_Angeles:20250625T134500
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UID:dac_DAC 2025_sess143_RESEARCH2126@linklings.com
SUMMARY:DCO-3D: Differentiable Congestion Optimization in 3D ICs
DESCRIPTION:Hao-Hsiang Hsiao (Georgia Institute of Technology), Yi-Chen Lu
  (Nvidia), Pruek Vanna-iampikul (Burapha University), Anthony Agnesina and
  Rongjian Liang (Nvidia), Yuan-Hsiang Lu (Georgia Institute of Technology)
 , Haoxing Ren (Nvidia), and Sung Kyu Lim (Georgia Institute of Technology)
 \n\nState-of-the-art 3D IC flows fail to consider 3D congestion during ear
 lier stages, leading to excessive use of end-of-flow ECO resources for rou
 tability correction that severely degrades full-chip Power, Performance, a
 nd Area metrics. We present DCO-3D, a Machine Learning based routability-a
 ware 3D PD flow that performs early post-route congestion prediction using
  Siamese Networks and resolves the predicted hotspots using a fully differ
 entiable 3D cell spreading with Graph Neural Network. On 6 industrial desi
 gns in a commercial 3nm node, DCO-3D improves Pin-3D, the known best Pin-3
 D flow, by up to 47.2% in overflow, 86.2% in TNS and 5.1% in power at sign
 off.\n\nTopics: EDA\n\nTracks: EDA7: Physical Design and Verification\n\nS
 ession Chairs: Igor Markov (Synopsys) and David Chinnery (Siemens)\n\n
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