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DTSTART;TZID=America/Los_Angeles:20250625T144500
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UID:dac_DAC 2025_sess143_RESEARCH729@linklings.com
SUMMARY:FedEDA: Federated Learning Framework for Privacy-Preserving Machin
 e Learning in EDA
DESCRIPTION:JoonSeok Kim, Donggyu Kim, Seonghyeon Park, and Seokhyeong Kan
 g (Pohang University of Science and Technology (POSTECH))\n\nIn advanced n
 odes, the optimization of Power, Per- formance, and Area (PPA) is becoming
  increasingly complex, requiring significant resources and time for circui
 t design and optimization using Electronic Design Automation (EDA). As a k
 ey approach to overcome these challenges, Machine Learning (ML) techniques
  have been widely studied in the field of EDA. However, security concerns 
 around Intellectual Property (IP) limit access to real-world circuit data,
  making it difficult to gather sufficient data for training ML models. Thi
 s lack of available circuit benchmarks restricts progress in ML research. 
 In this study, we propose FedEDA, which, to the best of our knowledge, is 
 the first Federated Learning (FL) aggregation algorithm specifically desig
 ned for EDA. FedEDA addresses concerns about IP security by exchanging mod
 el weights among FL participants instead of sharing raw data. Furthermore,
  FedEDA leverages Rent's Rule and circuit size to capture the hierarchical
  structure of circuits, mitigating issues related to data imbalance among 
 participants and improving the quality of weight aggregation on EDA data. 
 We demonstrate the applicability of FedEDA across various EDA tasks, inclu
 ding routability, parasitic RC, and wirelength prediction. FedEDA outperfo
 rms existing FL algorithms in EDA tasks, demonstrating superior performanc
 e.\n\nTopics: EDA\n\nTracks: EDA7: Physical Design and Verification\n\nSes
 sion Chairs: Igor Markov (Synopsys) and David Chinnery (Siemens)\n\n
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