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DTSTAMP:20260402T024506Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T103000
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UID:dac_DAC 2025_sess144@linklings.com
SUMMARY:Adventures in PCBs, Partitioning, and Legalization!
DESCRIPTION:Buckle up for an adventure through the realms of PCBs, partiti
 oning, and legalization! Start by exploring novel algorithms for PCB globa
 l placement and legalization. Next, dive into a GNN-based graph partitioni
 ng algorithm, followed by a fast deterministic parallel hypergraph partiti
 oner. Then, explore multi-height cell legalization with TSMC's recent FinF
 lex standard cells that allows for better PPA. End your journey with a det
 ailed placer that optimizes secondary power delivery network for multi-pow
 er domain designs.\n\nConstraint Graph-based PCB Legalization Considering 
 Dense, Heterogeneous, Irregular-Shaped, and Any-Oriented Components\n\nIn 
 modern printed circuit board (PCB) designs, the increasing complexity pose
 s more challenges for automatic placement. Existing PCB placement methods 
 cannot handle complex constraints with heterogeneous, irregular-shaped, an
 d any-oriented components for double-sided PCB designs well. This paper pr
 o...\n\n\nChiao-Yu Ou, Yan-Jen Chen, and Yao-Wen Chang (National Taiwan Un
 iversity)\n---------------------\nBlasPart: A Deterministic Parallel Parti
 tioner for Balanced Large-Scale Hypergraph Partitioning\n\nBalanced hyperg
 raph partitioning is a fundamental problem in applications like VLSI desig
 n, high-performance computing, etc. Nowadays, large-scale hypergraphs beco
 me more common due to the increasing complexity of modern systems. Thus, f
 ast and high-quality deterministic partitioning algorithms are ...\n\n\nSh
 engbo Tong, Chunyan Pei, and Wenjian Yu (Tsinghua University)\n-----------
 ----------\nClearance-Constrained PCB Global Placement with Heterogeneous 
 Components\n\nThe complexity of design rules and intense time-to-market de
 mands have made auto-placement tools essential for advanced printed circui
 t board (PCB) designs. This paper presents a novel PCB placement framework
  to handle pad-to-pad clearance constraints and heterogeneous components t
 o address these ch...\n\n\nYan-Jen Chen, Wei-Kai Huang, Chung-Ting Tsai, C
 hiao-Yu Ou, and Yao-Wen Chang (National Taiwan University)\n--------------
 -------\nGPart: A GNN-Enabled Multilevel Graph Partitioner\n\nGPart is a s
 calable multilevel framework for graph partitioning that integrates GNN em
 beddings with efficient coarsening and refinement techniques. On the Titan
 23 benchmarks, GPart achieves a cut size reduction of 34.13% to 42.92% ove
 r METIS and improves cut size by 9.30% on selected DIMACS benchmar...\n\n\
 nMagi Chen and Ting-Chi Wang (National Tsing Hua University)\n------------
 ---------\nMIA-aware FinFlex Cell Legalization with Power-Driven Cell Vers
 ion Substitution\n\nTSMC's FinFlex standard cells for sub-3 nm nodes provi
 de flexibility and an optimal balance of performance, power, and area. The
  FinFlex technology offers multiple versions per cell type with varied hei
 ghts and threshold voltages, allowing cell substitution for placement opti
 mization. This paper int...\n\n\nDa-Wei Huang and Shao-Yun Fang (National 
 Taiwan University of Science and Technology)\n---------------------\nSecon
 dary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs\
 n\nUsing multiple power domains is crucial for power savings in modern des
 igns, but advanced nodes face challenges in powering cross-domain cells du
 e to IR drop constraints and resource competition between secondary power 
 and signal routing. This paper presents a detailed placement method that i
 ntegrat...\n\n\nYu-Wei Chang and Shao-Yun Fang (National Taiwan University
  of Science and Technology) and Kai-Chuan Yang and Min-Ching Lin (Synopsys
 )\n\nTopics: EDA\n\nTracks: EDA7: Physical Design and Verification\n\nSess
 ion Chairs: Ankur Prasad (Apple Inc.) and Yu-Guang Chen (National Central 
 University)
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