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DTSTAMP:20260402T024534Z
LOCATION:3004\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T103000
DTEND;TZID=America/Los_Angeles:20250624T104500
UID:dac_DAC 2025_sess144_RESEARCH1761@linklings.com
SUMMARY:Clearance-Constrained PCB Global Placement with Heterogeneous Comp
 onents
DESCRIPTION:Yan-Jen Chen, Wei-Kai Huang, Chung-Ting Tsai, Chiao-Yu Ou, and
  Yao-Wen Chang (National Taiwan University)\n\nThe complexity of design ru
 les and intense time-to-market demands have made auto-placement tools esse
 ntial for advanced printed circuit board (PCB) designs. This paper present
 s a novel PCB placement framework to handle pad-to-pad clearance constrain
 ts and heterogeneous components to address these challenges. Unlike existi
 ng academic placers, our framework focuses on the following key features: 
 a wire-area model to account for various routing resource needs between po
 wer and signal nets, a pad-to-pad clearance model to minimize spacing viol
 ations, and a two-sided, pad-type-aware density model to reduce component 
 and pad overlap. We further develop a quadratic programming-based legalize
 r to resolve constraint violations among components of varying shapes. Exp
 erimental results show the effectiveness and efficiency of our framework, 
 surpassing two state-of-the-art academic placers in post-routing quality o
 n both academic and industrial benchmarks.\n\nTopics: EDA\n\nTracks: EDA7:
  Physical Design and Verification\n\nSession Chairs: Ankur Prasad (Apple I
 nc.) and Yu-Guang Chen (National Central University)\n\n
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