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UID:dac_DAC 2025_sess150_RESEARCH883@linklings.com
SUMMARY:FastPath: A Hybrid Approach for Efficient Hardware Security Verifi
 cation
DESCRIPTION:Lucas Deutschmann (RPTU Kaiserslautern-Landau); Andres Meza (U
 niversity of California, Santa Barbara); Dominik Stoffel and Wolfgang Kunz
  (RPTU Kaiserslautern-Landau); and Ryan Kastner (University of California,
  Santa Barbara)\n\nIn response to the surge of security breaches in hardwa
 re designs, many verification methods have been proposed to detect microar
 chitectural information leakage. These sophisticated efforts have gone a l
 ong way toward preventing attackers from breaking the confidentiality of t
 he system. However, each approach comes with its own set of weaknesses: it
  may not be\nscalable enough, it may not be exhaustive, it may not be flex
 ible enough to meet changing requirements, or it may not fit well\ninto ex
 isting verification flows.\nIn this paper, we propose FastPath, a hybrid v
 erification methodology that leverages the strengths of different approach
 es while compensating their weaknesses. In particular, it combines the eff
 iciency of simulation with the exhaustive nature of formal verification. I
 n addition, FastPath employs a structural analysis framework to automate t
 he method further. Our experimental results compare FastPath to a state-of
 -the-art formal approach, showing a significant reduction in manual effort
  while achieving the same level of exhaustive confidence. We also discover
 ed and contributed a fix for a previously unknown leak of internal operand
 s in cv32e40s, a RISC-V processor intended for security applications.\n\nT
 opics: Security\n\nTracks: SEC2: Hardware Security: Primitives & Architect
 ure, Design & Test\n\nSession Chairs: Gang Qu (University of Maryland) and
  Qian Wang (Intel Corporation)\n\n
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