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DTSTAMP:20260402T024533Z
LOCATION:3008\, Level 3
DTSTART;TZID=America/Los_Angeles:20250623T161500
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UID:dac_DAC 2025_sess156_RESEARCH960@linklings.com
SUMMARY:VersaSlot: Efficient Fine-grained FPGA Sharing with Big.Little Slo
 ts and Live Migration in FPGA Cluster
DESCRIPTION:Jianfeng Gu, Hao Wang, Xiaorang Guo, Martin Schulz, and Michae
 l Gerndt (Technical University of Munich)\n\nAs FPGAs gain popularity for 
 on-demand application acceleration in data center computing, dynamic parti
 al reconfiguration (DPR) has become an effective fine-grained sharing tech
 nique for FPGA multiplexing. However, current FPGA sharing encounters part
 ial reconfiguration contention and task execution blocking problems introd
 uced by the DPR, which significantly degrade application performance. In t
 his paper, we propose VersaSlot, an efficient spatio-temporal FPGA sharing
  system with novel Big.Little slot architecture that can effectively resol
 ve the contention and task blocking while improving resource utilization. 
 For the heterogeneous Big.Little architecture, we introduce an efficient s
 lot allocation and scheduling algorithm, along with a seamless cross-board
  switching and live migration mechanism, to maximize FPGA multiplexing acr
 oss the cluster. We evaluate the VersaSlot system on an FPGA cluster compo
 sed of the latest Xilinx UltraScale+ FPGAs (ZCU216) and compare its perfor
 mance against four existing scheduling algorithms. The results demonstrate
  that VersaSlot achieves up to 13.66x lower average response time than the
  traditional temporal FPGA multiplexing, and up to 2.19x average response 
 time improvement over the state-of-the-art spatio-temporal sharing systems
 . Furthermore, VersaSlot enhances the LUT and FF resource utilization by 3
 5% and 29% on average, respectively.\n\nTopics: Systems\n\nTracks: SYS2: D
 esign of Cyber-Physical Systems and IoT\n\nSession Chairs: Stefano Di Carl
 o (Politecnico di Torino) and Hokeun Kim (Arizona State University)\n\n
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