BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:3008\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T154500
DTEND;TZID=America/Los_Angeles:20250624T160000
UID:dac_DAC 2025_sess157_RESEARCH692@linklings.com
SUMMARY:An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acce
 leration
DESCRIPTION:Xianhao He, Haotian Wang, Jiapeng Zhang, and Wangdong Yang (Hu
 nan University); Anthony Chronopoulos (The University of Texas at San Anto
 nio); and Kenli Li (Hunan University)\n\nSparsity is widely prevalent in r
 eal-world applications, yet existing compiler optimizations and code gener
 ation techniques for sparse computations remain underdeveloped. Sparse mat
 rix-matrix multiplication (SpMM) is a representative operator in sparse co
 mputations, whose performance is often limited by the design of sparse for
 mats and the extent of hardware architecture optimization. Most existing s
 olutions achieve high-performance SpMM through two approaches: (1) meticul
 ously designed kernels and specialized sparse formats, which require exten
 sive manual effort, or (2) tensor compilers that support code generation, 
 though these typically offer limited support for sparse patterns, making i
 t challenging to adapt to complex sparsity patterns in practical applicati
 ons. This paper presents SpMMTC, an input-aware sparse tensor compiler. Gi
 ven a sparse matrix as input, SpMMTC analyzes its non-zero distribution an
 d generates a vectorized kernel optimized for SpMM on the specific matrix.
  We evaluated SpMMTC on various workloads. It achieves speedups of 1.21x t
 o 2.97x over state-of-the-art methods such as TACO, TVM, and ASpT on diffe
 rent multi-core processors. It also provides an speedup of up to 1.52x for
  sparse MobileNetV1 inference on the edge device.\n\nTopics: Systems\n\nTr
 acks: SYS3: Embedded Software\n\nSession Chairs: Hoeseok Yang (Santa Clara
  University) and Younghyun Kim (Purdue University)\n\n
END:VEVENT
END:VCALENDAR