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DTSTAMP:20260402T024533Z
LOCATION:3008\, Level 3
DTSTART;TZID=America/Los_Angeles:20250623T143000
DTEND;TZID=America/Los_Angeles:20250623T144500
UID:dac_DAC 2025_sess160_RESEARCH955@linklings.com
SUMMARY:Expanding Logical Space Freely: A Memory-efficient Mapping Table D
 esign for Compressional SSDs
DESCRIPTION:Zixuan HUANG (The Chinese University of Hong Kong); Tianyu Wan
 g (Shenzhen University); and Kecheng HUANG, Zelin Du, and Zili Shao (The C
 hinese University of Hong Kong)\n\nCompressional SSDs can be a mixed bless
 ing. While they offer users increased logical space beyond the physical ca
 pacity, they also complicate the internal design of the Flash Translation 
 Layer (FTL) by requiring a larger Logical-to-Physical (L2P) address mappin
 g.\n\nIn this paper, we propose a novel N-to-1 L2P mapping table design th
 at consolidates multiple logical entries into a single entry. This approac
 h eliminates the duplication of physical page numbers when a physical page
  contains several compressed logical pages, significantly reducing the mem
 ory footprint of compressional SSDs.To accommodate the dynamic compression
  ratios of real-world workloads, we introduce promotion and demotion schem
 es that enable mapping table entries to migrate between pages with differe
 nt compression ratios. Additionally, to address the issue of partial inval
 idation—where some compressed logical pages within a physical page are inv
 alid due to the N-to-1 mapping—we present a compression-aware garbage coll
 ection (GC) algorithm aimed at minimizing the number of copy operations fo
 r partially invalid physical pages.\n\nWe have implemented our design in M
 Qsim, a widely used SSD simulator, and have conducted a series of experime
 nts to evaluate the effectiveness of the proposed techniques. The results 
 demonstrate that our approach significantly reduces the mapping table size
  in compressional SSDs, leading to an improved mapping table cache hit rat
 io and a reduced I/O latency compared to traditional compressional SSDs.\n
 \nTopics: Systems\n\nTracks: SYS5: Embedded Memory and Storage Systems\n\n
 Session Chairs: Chun-Feng Wu (National Yang Ming Chiao Tung University) an
 d Yi Wang (Shenzhen University)\n\n
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