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DTSTART:19700308T020000
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DTSTAMP:20260402T024534Z
LOCATION:2008\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T160000
DTEND;TZID=America/Los_Angeles:20250624T161500
UID:dac_DAC 2025_sess214_ENGPRES317@linklings.com
SUMMARY:Improving Functional Accuracy of Virtual Platform Based on Coreles
 s Test Framework in Early Development Stage
DESCRIPTION:jaeyeong jeon, Sangwoo Han, Jooho Wang, Seungik Ha, Jinbeom Ki
 m, Myeongjin Kim, Jongseong Park, Kyungsu Kang, and Silwan Chang (Samsung)
 \n\nIn conventional embedded SoC development, SW development is tightly co
 upled with release plan of HW prototype.\nVirtual Platform (VP) enables so
 ftware developers to kick-off their developments at the earlier stage than
  before. However, In the early development stage, VP dose not guarantee th
 e functional accuracy.\nIn previous, Test-FW for HW prototype was reused f
 or VP verification, so VP release timing is delayed due to Test-FW prepara
 tion.\nIn this paper, we propose Coreless Test Framework (CTF) which is si
 mple and light verification method using custom Verification IP.\nVerifica
 tion utilizing Test-FW is a complex and time consuming work, as it require
 s many essential IPs for operating the processor, such as the ARM core, me
 mory, and their corresponding interfaces.\nThe CTF is significantly simpli
 fied as it does not require the implementation of the core model's complex
 ities and increase the firmware verification coverage of the early-stage V
 P by up 2.4.\n\nTopics: AI, Systems and Software\n\nSession Chairs: Jakob 
 Engblom (Intel Corporation) and Natraj Ekambaram\n\n
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