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DTSTAMP:20260402T024507Z
LOCATION:2008\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T153000
DTEND;TZID=America/Los_Angeles:20250623T170000
UID:dac_DAC 2025_sess215@linklings.com
SUMMARY:Back-end and System Considerations for Chiplets
DESCRIPTION:Join us for a comprehensive session that explores the latest a
 dvancements in chiplet integration and 3DIC design, focusing on security, 
 optimization, and thermal management, offering valuable insights into cutt
 ing-edge methodologies that enhance the reliability, efficiency, and perfo
 rmance of modern SoC and 3DIC systems. We start with a deep dive into secu
 re chiplet integration within System-in-Package (SiP) architectures, detai
 ling methods for secure authentication, remote attestation, and data prote
 ction through cryptographic techniques. Next, discover how to leverage mac
 hine learning to optimize heterogeneous 3DIC designs, significantly enhanc
 ing power, performance, and area (PPA) metrics through automated design sp
 ace exploration. Explore SuperCoverage, an AI-guided approach that exponen
 tially increases workload coverage for power and thermal analysis, ensurin
 g accurate hot-spot temperature measurements crucial for dynamic power and
  thermal control. Learn about the complexities of Electrostatic Discharge 
 (ESD) in multi-die systems, and learn how novel simulation tools can ident
 ify potential ESD vulnerabilities in 3DIC designs. This session will also 
 cover advanced thermal simulation techniques for 3DIC packages with co-pac
 kaged optics, addressing thermal cross-talk and ensuring thermal integrity
 . Lastly, discover high-performance extraction methods for 2.5D/3D-IC pack
 ages, utilizing hybrid computational electromagnetic frameworks and machin
 e learning to streamline the design process.\n\nAnalysis of Electrostatic 
 Discharge (ESD) for 3DIC systems\n\nElectrostatic Discharge (ESD) poses ne
 w challenges in multi-die (2.5D and 3D) systems. Traditional ESD analysis 
 focuses on single-die systems, but multi-die systems introduce new dischar
 ge paths from die-to-die, necessitating a comprehensive assessment through
  simulation. This study applies well-est...\n\n\nAnila Azam (Intel Corpora
 tion)\n---------------------\nAccurate Thermal Simulation of 3DIC Package 
 with Co-Packaged Optics\n\nCo-packaged optics (CPO) is a promising candida
 te for implementing low-power, high-bandwidth optical links in datacenters
  and in high-performance computing (HPC) systems. By bringing the optical 
 transceiver into the 3DIC package, CPO can reduce the complexity and power
  loss of the overall system.  T...\n\n\nAhsan Alam, Qinglian Li, Lucy Yin,
  Lang Lin, and Wenbo Xia (Ansys)\n---------------------\nSecuring Chiplet 
 Integration: A System-in-Package Security Architecture.\n\nChiplets enable
  a new design methodology where monolithic System-on-Chips (SoCs) are disa
 ggregated into several chip(let)s integrated together within a System-in-P
 ackage (SiP).\n\nThe ultimate achievement in this respect is the ability t
 o mix and match heterogeneous chiplets (in different technologies...\n\n\n
 Sylvain Guilley (Secure-IC) and Junie Um (Cadence Design Systems, Inc.)\n-
 --------------------\nSuperCoverage: AI-Guided Full Coverage of Thermal an
 d Power Analysis for SoC Design\n\nTransient temperature response approxim
 ately follows an exponential function of power density. As transistors kee
 p shrinking due to Moore's Law turbo workloads in client processors are ex
 periencing increased localized power density – resulting in increased tran
 sient temperature ramp rates and large ...\n\n\nXia Zhu, Jianfang Zhu, Mar
 k Gallina, and Julien Sebot (Intel Corporation)\n---------------------\nHe
 terogenous 3DIC Partitioning with Cerebrus Machine Learning for PPA optimi
 zation\n\nIn recent years, 3D design disaggregation has become instrumenta
 l in improving wafer cost, yields, design flexibility, PPA (power, perform
 ance, area). To fully realize the benefits of 3D disaggregation, it is alw
 ays desired to have a heterogenous 3DIC system, where each die uses a diff
 erent process ...\n\n\nYi-Wei Chen, Chung-Ching Peng, Yi-Shan Li, Kuan-Tin
 g Kuo, and Vivek Rajan (Intel Corporation) and Narendra Akilla, Stephen Mo
 rais, Xukang Wu, Naresh Mummidivarapu, and Kumar Subramani (Cadence Design
  Systems, Inc.)\n---------------------\nHigh Performance Extraction of 2.5
 D/3D-IC Package\n\nThe need for modern workloads in the latest innovations
  has brought 2.5D/3D stacking and advanced IC packaging technologies to th
 e forefront. The requirements for integrating multiple chips, components, 
 and materials to create an advanced IC package are becoming increasingly c
 omplicated and introduc...\n\n\nXiaoyan Xiong, Yingxin Sun, Jiyue Zhu, Gan
 g Kang, and Jian Liu (Cadence Design Systems, Inc.)\n\nTopics: AI, Systems
  and Software, Chiplet\n\nSession Chair: Frank Schirrmeister (Synopsys)
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