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DTSTART;TZID=America/Los_Angeles:20250623T154500
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UID:dac_DAC 2025_sess215_ENGPRES054@linklings.com
SUMMARY:Heterogenous 3DIC Partitioning with Cerebrus Machine Learning for 
 PPA optimization
DESCRIPTION:Yi-Wei Chen, Chung-Ching Peng, Yi-Shan Li, Kuan-Ting Kuo, and 
 Vivek Rajan (Intel Corporation) and Narendra Akilla, Stephen Morais, Xukan
 g Wu, Naresh Mummidivarapu, and Kumar Subramani (Cadence Design Systems, I
 nc.)\n\nIn recent years, 3D design disaggregation has become instrumental 
 in improving wafer cost, yields, design flexibility, PPA (power, performan
 ce, area). To fully realize the benefits of 3D disaggregation, it is alway
 s desired to have a heterogenous 3DIC system, where each die uses a differ
 ent process technology with its unique advantages that are most suitable f
 or the designs on such die. Historically, the selection of heterogenous 3D
  disaggregation design boundaries, or "cutlines", are usually determined i
 n a holistic way that may be tedious and unoptimized, and each die was opt
 imized separately as EDA tools generally do not support multiple process t
 echnologies during optimization. This would generally result in multiple t
 rials of cutline definition in order to obtain a satisfactory heterogenous
  3DIC system. Therefore, a better method to perform concurrent optimize  o
 n the entire heterogenous 3DIC design using multiple process technologies 
 with automation. In this work, we demonstrate an automated method to optim
 ize heterogenous 3DIC design PPA using Cadence Cerebrus to perform machine
  learning based design space exploration. With this methodology, concurren
 t optimization with multiple process technologies has ben achieved, and hu
 ndreds of 3DIC cutline experiments can be performed automatically and simu
 ltaneously, greatly reducing the time and effort needed to find an optimiz
 ed 3DIC cutline configuration. This Cerebrus-based methodology also consid
 ers all critical QOR metrics during optimization, such as areal density, m
 acro placements, bump assignment, timing closure, power consumption, IR dr
 op, and thermal dissipation. With this methodology, we are able to find hi
 ghly optimized heterogenous 3DIC designs with great efficiency and ease.\n
 \nTopics: AI, Systems and Software, Chiplet\n\nSession Chair: Frank Schirr
 meister (Synopsys)\n\n
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