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DTSTAMP:20260402T024533Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T141500
DTEND;TZID=America/Los_Angeles:20250624T143000
UID:dac_DAC 2025_sess218_ENGPRES244@linklings.com
SUMMARY:Formal signoff for Cross-Module Design logic: A novel approach to 
 manage formal scope in increasingly complex systems
DESCRIPTION:Sai Asrith Tabdil, Sakthivel Ramaiah, Clarice Oliveira, and So
 rna Inian (Cadence Design Systems, Inc.)\n\nIn today's complex IP design, 
 features span across multiple blocks to achieve a certain functionality. I
 t throws up challenges in formal verification to yield conclusive results 
 and coverage sign-off. Having multiple clocks and resets, handling constra
 ints are other concerns in the formal verification. As the feature spans a
 cross various blocks, there is a significant increase in the sequential de
 pth of the cone leading to undermined state for most of the properties. To
  overcome foresaid challenges, this paper talks about various nifty techni
 ques like Black Boxing, Abstractions, advanced AI/ML features like Proof M
 aster and functional coverage merge options. These techniques help in veri
 fying a complex feature in existing design or a new feature added to it.\n
 Methodologies and techniques outlined above were successfully applied to q
 ualify Compliance feature of USB 3.2 Controller. This feature is successfu
 lly verified with minimum number of undetermined properties. The functiona
 l coverage of formal is merged with simulation and the formal vPlan is bac
 k annotated with the master vPlan, to get the comprehensive verification t
 racking. With this formal approach we were able to expedite the verificati
 on process by x2 factor.\n\nTopics: Front-End Design\n\nSession Chair: Vik
 as Sachdeva (Real Intent)\n\n
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