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BEGIN:VEVENT
DTSTAMP:20260402T024532Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T163000
DTEND;TZID=America/Los_Angeles:20250623T164500
UID:dac_DAC 2025_sess219_ENGPRES169@linklings.com
SUMMARY:Robust Hard Macro Timing Validation: Early Detection of Issues and
  Automated Feedback for Integration
DESCRIPTION:Vaibhav Garg, Mohita Batra, Arjun Saha, and Rishabh Srivastava
  (Synopsys)\n\nImplementing designs with complex hard macros, like PHY sub
 systems, creates challenges for timing closure. Liberty models detail the 
 timing intent, requiring correct arcs for all interface data and clock por
 ts. At the integration level, understanding clock and data paths in these 
 hard macros can be overwhelming. Constraints linting and timing analysis t
 ools often miss issues like missing arcs, risking late detection of top-le
 vel timing problems or silicon failure if left unaddressed. For instance, 
 a missing arc on a clock port for a maximum frequency clock can lead to un
 der-constrained designs, while a missing data port arc may leave synchrono
 us paths untimed.\n\nThis paper proposes a utility for validating hard mac
 ro Liberty models against design goals and a dashboard to aid integrators 
 in establishing top-level constraints. The process involves designers gene
 rating a preliminary design intent in XLS format from the STA session, fol
 lowed by manual review to create a golden reference. Subsequent Liberty re
 visions are compared to this reference, highlighting discrepancies. Additi
 onally, the methodology generates a clock tree trace from the root to outp
 ut clock ports, pinpointing missing arcs. This approach leverages Synopsys
  PrimeTime along with Python and Perl scripts and is applicable to any har
 d macro design.\n\nTopics: IP\n\nSession Chair: Nanditha Rao (Indian Insti
 tute of Information Technology)\n\n
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