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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250625T114500
DTEND;TZID=America/Los_Angeles:20250625T120000
UID:dac_DAC 2025_sess220_ENGPRES194@linklings.com
SUMMARY:Reconfigurable Vector Floating Point Accelerator on FPGAs
DESCRIPTION:Himanshu Rai and Sasi Snigdha Yadavalli (International Institu
 te of Information Technology, Bangalore); Aishwarya Sridhar (Infineon Tech
 nologies); and Nanditha Rao (IBM)\n\nWe propose an architecture for accele
 rating floating point operations through a novel reconfigurable vector flo
 ating point design. This includes support for multiple precisions, includi
 ng the standard IEEE 754 Single (SP-32), Double (DP-64), Tensorfloat (TF-3
 2), Bfloat (BF-16), and custom configurations like Quarter precision (QP-8
 ). The architecture also introduces vector lane reconfiguration, allowing 
 for efficient parallelization  through packing and unpacking techniques. E
 ach vector lane can be adjusted at runtime on an FPGA, providing flexibili
 ty in supporting different unrolling factors for loop optimization. The de
 sign is implemented on AMD-Xilinx ZCU104 FPGA and integrates DSPs, optimiz
 ing LUT usage, power consumption, and performance. For example, SP-32 with
  DSP achieves a 31.6% reduction in LUT usage, a 9.3% increase in operating
  frequency, and 24.7% lower power consumption. We recommend DSP usage at h
 igher bit precisions. This flexibility in configuring precision levels all
 ows for efficient utilization of FPGA resources and energy-efficient desig
 n, especially for higher precision operations. Incorporating this design i
 nto AI/ML workflows, signal processing, and scientific computing accelerat
 es performance, providing a balance between throughput, power efficiency, 
 and computational complexity.\n\nTopics: IP\n\nSession Chair: Bhaskar Vedu
 la (Intel Corporation)\n\n
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