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DTSTART:19700308T020000
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DTSTAMP:20260402T024532Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250625T103000
DTEND;TZID=America/Los_Angeles:20250625T104500
UID:dac_DAC 2025_sess220_ENGPRES366@linklings.com
SUMMARY:Balancing Performance and Side-Channel Resilience in a Lightweight
  ECC Cryptosystem
DESCRIPTION:Harikrishnan Balagopal, Lang Lin, and Norman Chang (Ansys) and
  Mitra Mirhassani and Seyedeh Nejati (University of Windsor)\n\nBinary pol
 ynomial multipliers significantly influence the performance and cost effic
 iency of elliptic curve cryptography (ECC) systems. ECC hardware commonly 
 uses multiplication algorithms with sub quadratic complexity to minimize a
 rea usage and enhance speed. This research shows a new type of scalar poin
 t multiplication (SPM) processor for elliptic curves that uses a special g
 roup of overlap-free multipliers that work best for Internet of Things (Io
 T) uses. We design these multipliers to reduce partial products and employ
  overlap-free reconstruction methods, resulting in improved computational 
 recurrence and enhanced efficiency. \nThe designed ECC-Multiplier can be v
 ulnerable to power side channel leakage analysis if the RTL code has not b
 een validated by thorough security analysis. Through an automated power si
 de-channel leakage verification and root-causing flow, we demonstrated how
  to find the time and RTL gate with side-channel leakage of a unprotected 
 ECC design. This flow can help ECC designers assess the most secure implem
 entation and fix any leakage gate at early-stage RTL design phase.\n\nTopi
 cs: IP\n\nSession Chair: Bhaskar Vedula (Intel Corporation)\n\n
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