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DTSTART:19700308T020000
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DTSTAMP:20260402T024506Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T133000
DTEND;TZID=America/Los_Angeles:20250623T150000
UID:dac_DAC 2025_sess221@linklings.com
SUMMARY:Novel Eddies in the Implementation Flow
DESCRIPTION:A consistent and streamlined implementation flow is key for co
 mbining IP blocks into a working SoC and ensuring correct operation. This 
 session presents new approaches for timing closure, meso-synchronous clock
  domains, high level synthesis, modeling of clocks and reset, randomizing 
 memory content and managing large sets of simulation jobs.\n\nA novel appr
 oach to generate random/constrained Non-Volatile-Memory content in a UVM e
 nvironment\n\nVerifying a System on Chip (SoC) with embedded non-volatile 
 memory (NVM) requires numerous tests to cover a wide range of scenarios. T
 raditional methods involve manually setting NVM content or using custom sc
 ripts, which are labor-intensive and inflexible.\nWe developed an automate
 d flow that generat...\n\n\nDavide Sanalitro (STMicroelectronics)\n-------
 --------------\nCross-die timing methodology for Next-Gen Chiplet SOCs - A
  shift-left solution for cross-foundry 3DIC-STA Signoff\n\nAdoption of adv
 anced packaging has accelerated multi-chip module (MCM) based heterogeneou
 s SoC solutions. With standardization of Die to Die (D2D) interfaces such 
 as UCIe, Industry is aggressively designing Chiplet dies involving multipl
 e vendors, foundries, tech nodes and process corners. Due to sh...\n\n\nDe
 epon Saha, Animesh Sharma, Animesh Jain, Aniket Waghide, Dhruvin Shah, and
  Rajesh Anand (Advanced Micro Devices (AMD))\n---------------------\nNovel
  Clocks and Resets Architecture Model\n\nFunctional modeling is vital for 
 early System-on-Chip (SoC) validation, enabling architects to accurately r
 epresent design intent. However, modeling the Clock and Reset (CAR) unit—a
  critical component for synchronizing diverse SoC elements—faces significa
 nt challenges. These include mana...\n\n\nPreetika Tandon, Stephen Wang, a
 nd Mike Garrett (Nvidia)\n---------------------\nA Completely Digital, Low
 -Power, and Low-Area Phase Synchronization Architecture for Meso-Synchrono
 us Clock Domains Supporting Dynamic Frequency Scaling\n\nWhen multiple div
 ided clocks are derived from the same oscillator, and distributed across t
 he System on Chip(SOC) using different transistor families, it becomes ver
 y hard to balance the multiple clock trees.\nAll the divided clocks can th
 en be considered as mesochronous, i.e. the ratio between the c...\n\n\nAnu
 rag Choudhury, Robin Hoel, Aniruddha N, Abhishek Verma, and Abhinav Parash
 ar (Texas Instruments)\n---------------------\nOptimized Digital Design Fl
 ow for Embedded Sensor Applications Using High Level Synthesis\n\nIntegrat
 ing algorithms into sensors poses a significant challenge for designers. T
 echnological nodes are chosen for analog requirements, leaving limited spa
 ce for digital portion, which can not take advantage from technology scali
 ng. Digital designers are challenged with implementing on ASIC high-qu...\
 n\n\nMarco Castellano and Ugo Garozzo (STMicroelectronics)\n--------------
 -------\nAI-aided flow for digital verification of a multiprotocol SerDes 
 PHY\n\nThis work describes the development and implementation of a verific
 ation flow that is aided by Artificial Intelligence (AI), supported by Syn
 opsys VSO.ai.  A comparative analysis was made between the conventional an
 d the developed flow, on the verification of a multiprotocol SerDes PHY. \
 nCoverage cl...\n\n\nCelso Figueiredo and Domingos Terra (Synopsys)\n\nTop
 ics: AI, IP, Chiplet\n\nSession Chair: Shankar Hemmady (Micron Technology)
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