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BEGIN:VEVENT
DTSTAMP:20260402T024532Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T133000
DTEND;TZID=America/Los_Angeles:20250623T134500
UID:dac_DAC 2025_sess221_ENGPRES033@linklings.com
SUMMARY:Cross-die timing methodology for Next-Gen Chiplet SOCs - A shift-l
 eft solution for cross-foundry 3DIC-STA Signoff
DESCRIPTION:Deepon Saha, Animesh Sharma, Animesh Jain, Aniket Waghide, Dhr
 uvin Shah, and Rajesh Anand (Advanced Micro Devices (AMD))\n\nAdoption of 
 advanced packaging has accelerated multi-chip module (MCM) based heterogen
 eous SoC solutions. With standardization of Die to Die (D2D) interfaces su
 ch as UCIe, Industry is aggressively designing Chiplet dies involving mult
 iple vendors, foundries, tech nodes and process corners. Due to shorter in
 terconnect distance, these dies can communicate with each other using a so
 urce-synchronous clock-forwarding architecture PHY. Effectively making a l
 aunch & capture cross-die timing path originating at one die and ending at
  the other. \nDue to lack of proper cross-die STA signoff methodology, we 
 are forced to adopt pessimistic guard-banding approach, which won't scale 
 correctly with higher data rates. A new methodology for design & signoff a
 t package level is the need of the hour. Link budgeting based on channel I
 SI/cross-talk/jitter and eye-plot are still integral part of the design fl
 ow. However, the silicon correlation data did show that power-efficient so
 urce-synchronous short-reach PHY can open the possibility of STA margining
  methodology accounting for all the error components of link budget in fut
 ure, leading to a new era of shift-left automation in custom work force.\n
 The proposed 3DIC STA solution is foundry, tech-node and process agonistic
  – thereby enabling universal interoperability at Chiplet package level al
 ong with silicon proven accuracy.\n\nTopics: AI, IP, Chiplet\n\nSession Ch
 air: Shankar Hemmady (Micron Technology)\n\n
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