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DTSTART:19700308T020000
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DTSTAMP:20260402T024532Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T143000
DTEND;TZID=America/Los_Angeles:20250623T144500
UID:dac_DAC 2025_sess221_ENGPRES036@linklings.com
SUMMARY:A novel approach to generate random/constrained Non-Volatile-Memor
 y content in a UVM environment
DESCRIPTION:Davide Sanalitro (STMicroelectronics)\n\nVerifying a System on
  Chip (SoC) with embedded non-volatile memory (NVM) requires numerous test
 s to cover a wide range of scenarios. Traditional methods involve manually
  setting NVM content or using custom scripts, which are labor-intensive an
 d inflexible.\nWe developed an automated flow that generates random or con
 strained NVM content to verify all possible values, and allows easy modifi
 cation based on specific tests.\nOur approach uses a spreadsheet to define
  NVM structure, read by an open-source language to generate a UVM Verifica
 tion IP (VIP) with the expected memory structure and covergroups. This VIP
  automatically constructs NVM content sector by sector, eliminating manual
  bit-by-bit modifications. Additional files handle data constraints and ra
 ndomization, used by the simulator in specific UVM phases to generate the 
 NVM data. \nThis method provides control over NVM content within the UVM f
 ramework, independent of simulation tools and programming languages. It ac
 hieves comprehensive coverage and drastically reduces the time required fo
 r generating NVM content. The innovative approach enhances silicon quality
  and prevents bugs, making it a versatile solution for any project.\n\nTop
 ics: AI, IP, Chiplet\n\nSession Chair: Shankar Hemmady (Micron Technology)
 \n\n
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