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DTSTAMP:20260402T024533Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T134500
DTEND;TZID=America/Los_Angeles:20250623T140000
UID:dac_DAC 2025_sess221_ENGPRES062@linklings.com
SUMMARY:A Completely Digital, Low-Power, and Low-Area Phase Synchronizatio
 n Architecture for Meso-Synchronous Clock Domains Supporting Dynamic Frequ
 ency Scaling
DESCRIPTION:Anurag Choudhury, Robin Hoel, Aniruddha N, Abhishek Verma, and
  Abhinav Parashar (Texas Instruments)\n\nWhen multiple divided clocks are 
 derived from the same oscillator, and distributed across the System on Chi
 p(SOC) using different transistor families, it becomes very hard to balanc
 e the multiple clock trees.\nAll the divided clocks can then be considered
  as mesochronous, i.e. the ratio between the clocks is known and the phase
  is unknown but constant.\nBy treating the 2 clock domains as mesochronous
  instead of asynchronous, we can easily increase the throughput of the dat
 a crossing the mesochronous domains.\nThis work proposes a phase synchroni
 zation architecture for mesochronous clock domains, which has been develop
 ed from ground up and is completely digital.\nThe proposed architecture is
  very different from the present literature and caters to low power and lo
 w area SOCs and is independent of any gate level custom analog designs or 
 technology node.\nThe proposed phase synchronization scheme can be adjuste
 d for any clock ratio on the fly and is also suitable for sporadic data tr
 ansfers and not just burst data, thus providing a versatile solution.\nThe
  principles of phase detect synchronization is described with respect to A
 RM's AHB-APB mesochronous bridge, but can be easily extended to sample any
  data signal crossing mesochronous domains.\n\nTopics: AI, IP, Chiplet\n\n
 Session Chair: Shankar Hemmady (Micron Technology)\n\n
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