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DTSTAMP:20260402T024533Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T141500
DTEND;TZID=America/Los_Angeles:20250623T143000
UID:dac_DAC 2025_sess221_ENGPRES245@linklings.com
SUMMARY:Novel Clocks and Resets Architecture Model
DESCRIPTION:Preetika Tandon, Stephen Wang, and Mike Garrett (Nvidia)\n\nFu
 nctional modeling is vital for early System-on-Chip (SoC) validation, enab
 ling architects to accurately represent design intent. However, modeling t
 he Clock and Reset (CAR) unit—a critical component for synchronizing diver
 se SoC elements—faces significant challenges. These include managing multi
 ple reset and clock domains, aligning them with initialization requirement
 s, ensuring precise synchronization, and integrating power, safety, and re
 liability features while adhering to platform-specific constraints.\n\nDes
 pite the availability of detailed architecture specifications, these are n
 ot directly translatable into functional models. This results in manual, e
 rror-prone processes, misalignment between functional models and architect
 ure intent, and delays in achieving crucial design and validation mileston
 es.\n\nWe propose an automated approach to create a self-checking, executa
 ble model directly derived from architecture specifications. This approach
  ensures seamless inheritance of clock and reset requirements, bridging th
 e gap between architecture and functional modeling. By automating this pro
 cess, we reduce errors, accelerate development, and maintain alignment acr
 oss architecture and design stages. The solution is scalable and efficient
 , with applications extending to SystemC model development, power architec
 ture specification, physical design timing analysis, RTL design, and verif
 ication domains.\n\nTopics: AI, IP, Chiplet\n\nSession Chair: Shankar Hemm
 ady (Micron Technology)\n\n
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