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BEGIN:VEVENT
DTSTAMP:20260402T024532Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T140000
DTEND;TZID=America/Los_Angeles:20250623T141500
UID:dac_DAC 2025_sess221_ENGPRES345@linklings.com
SUMMARY:Optimized Digital Design Flow for Embedded Sensor Applications Usi
 ng High Level Synthesis
DESCRIPTION:Marco Castellano and Ugo Garozzo (STMicroelectronics)\n\nInteg
 rating algorithms into sensors poses a significant challenge for designers
 . Technological nodes are chosen for analog requirements, leaving limited 
 space for digital portion, which can not take advantage from technology sc
 aling. Digital designers are challenged with implementing on ASIC high-qua
 lity algorithms in terms of accuracy while minimizing area and power consu
 mption. Our proposal introduces a flow based on modular blocks called "Bri
 cks", which have both SystemC and Python views. This approach allows the a
 nalysis of how to best connect and configure these Bricks using Python lib
 raries, while also providing feedback to the High-Level Synthesis (HLS) to
 ol. This Python-HLS loop optimizes power, area, latency, and accuracy in a
  multi-objective optimization process. The proposed flow reduces time to m
 arket and enables the best choice among various options. By leveraging the
  use of Python the flow offers flexibility and configurability, allowing f
 or the utilization of a wide range of libraries and tools. Continuous feed
 back to the HLS tool facilitates rapid iterations and incremental improvem
 ents.\nThe results in a specific case for a people counter on an infrared 
 image sensor demonstrate the effectiveness of the flow in providing excell
 ent solutions in terms of both accuracy and area, significantly reducing t
 he IP development time.\n\nTopics: AI, IP, Chiplet\n\nSession Chair: Shank
 ar Hemmady (Micron Technology)\n\n
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