BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024532Z
LOCATION:2010\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T114500
DTEND;TZID=America/Los_Angeles:20250623T120000
UID:dac_DAC 2025_sess222_ENGPRES235@linklings.com
SUMMARY:Advanced Verification Solutions for Communication ICs to Ensure Hi
 gh Quality Amid PVT Variations
DESCRIPTION:Tomohiro Ishida and Shunichi Kobo (THine Electronics) and Yuli
 ng Lin and Lih-Jen Hou (Siemens)\n\nTHine Electronics specializes in desig
 ning high-speed interfaces and timing controllers. Their newly developed I
 C features 8-bit x 8 phase interpolators, designed for high-speed IO inter
 faces and communication systems. To ensure the quality of this design, THi
 ne's design flow demands SPICE-accurate verification across a wide range o
 f scenarios, including 64 process modes, multiple temperature and supply v
 oltage values, and hundreds of phase interpolator settings. This results i
 n tens of thousands of nominal corners, requiring a significant number of 
 samples for achieving 4-sigma statistical accuracy. Traditional methods wo
 uld need at least 10 million samples for verification. \nTo meet their ver
 ification goals within practical production timelines, THine Electronics u
 tilized an AI-driven methodology incorporating Siemens' Solido Simulation 
 Suite and Solido Design Environment. This approach allowed the design team
  to secure SPICE-accurate verification at 4-sigma with only thousands of s
 amples, reducing the total verification cycle by 100x in terms of simulati
 on numbers compared to conventional brute-force methods. \nIn this present
 ation, we will explore the complex verification challenges encountered, th
 e methodology used to overcome them, and the achieved results, highlightin
 g how the collaboration between THine Electronics and Siemens EDA leverage
 d an AI-powered design verification flow to achieve accurate results with 
 remarkable efficiency gains.\n\nTopics: AI, IP\n\nSession Chair: Navid Far
 azmand (Google)\n\n
END:VEVENT
END:VCALENDAR