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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T110000
DTEND;TZID=America/Los_Angeles:20250624T111500
UID:dac_DAC 2025_sess223_ENGPRES018@linklings.com
SUMMARY:Enhancing PDK Library Validation with Machine Learning. A Novel Ap
 proach to Layout Comparison
DESCRIPTION:Nolan Pavek, Romain Feuillette, and Farzana Akhter (GlobalFoun
 dries)\n\nMaintaining the accuracy and consistency of Process Design Kits 
 (PDKs) in the rapidly evolving semiconductor design industry is critical f
 or ensuring high-quality integrated circuit (IC) production. Conventional 
 techniques for PDK library comparisons, like rule-based checks and manual 
 inspections, take a lot of time and are prone to human mistakes. \nMore sp
 ecifically, PDK models are based on silicon data from "Golden GDS" layouts
 , which serve as the benchmark for model accuracy. As a device evolves, it
 s physical layout (PCell) may need updates to accommodate model fine tunin
 g or improve performance. Ensuring these updates remain consistent with th
 e original Golden GDS is crucial for maintaining model accuracy.\nThis pap
 er presents a novel method to improve the internal layout comparison of PD
 K libraries using machine learning. A regular XOR comparison between the g
 olden GDS and the reference GDS would yield a lot of false errors and the 
 manual review of layout variations during the lifecycle is time consuming 
 and resource intensive to categorize changes as either expected or unexpec
 ted. Our novel approach, however, achieves considerable improvements in ef
 ficiency and reliability by streamlining the discovery of inconsistencies 
 within PDK libraries through multiple supervised machine learning techniqu
 es.\n\nTopics: AI, Back-End Design\n\nSession Chair: Shane Stelmach (Texas
  Instruments)\n\n
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