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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T113000
DTEND;TZID=America/Los_Angeles:20250624T114500
UID:dac_DAC 2025_sess223_ENGPRES058@linklings.com
SUMMARY:Generation of Failure Inspection Pattern without Design Impact dur
 ing P&R in BSPDN Design
DESCRIPTION:Woojin Jin, Sangun Park, Joowan Lee, Haemin Yoo, and TaeYang Y
 OU (Samsung)\n\nThis paper presents an effective and efficient design meth
 od for inserting failure inspection patterns at BSPDN (Back-Side Power Del
 ivery Network) designs. BSPDN designs provide more signal resources and mi
 tigate IR-drop during front-side design, resulting in better power integri
 ty and improved performance. However, since the conventional silicon failu
 re inspection method of FSPDN (Front-Side Power Delivery Network) cannot b
 e used, an appropriate method is required to inspect failures in silicon. 
 In this paper, two insertion method for failure inspection have been repre
 sented. One method is to use inspection patterns of the topmost routing la
 yer for electrical failure inspection (EFI). The topmost inspection patter
 ns are connected to the target nets with the conventional auto routing met
 hod without changing the existing signal routings of the nets. The other o
 ne is die-lens, which is an empty metal-free region, for optical failure i
 nspection (OFI). These two efficient failure inspection patterns can be us
 ed at the wafer or package level to investigate silicon failure point. We 
 have designed a BSPDN test vehicle using the proposed method and obtained 
 satisfactory results.\n\nTopics: AI, Back-End Design\n\nSession Chair: Sha
 ne Stelmach (Texas Instruments)\n\n
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