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DTSTART:19700308T020000
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DTSTAMP:20260402T024511Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T133000
DTEND;TZID=America/Los_Angeles:20250623T150000
UID:dac_DAC 2025_sess224@linklings.com
SUMMARY:Grid Resilience - Powering Solutions Design and Delivery for the P
 erformance Promises
DESCRIPTION:Power keeps the engine humming and delivering promised perform
 ance. Learn from others that have modeled power delivery early to signoff 
 and doing it smart - Multi-die to ML driven with an eye for analytical spe
 ed is the focus of this session.\n\nIR Drop-Aware PDN Design Methodology f
 or HBM Proxy Package Si-Interposer with 3D-IC Platform\n\nAs the number of
  AI parameters increases, the need for 2.5D packaging, including multi-HBM
 , becomes more necessary. There are more than 12,000 bumps in a single HBM
 , increasing the design complexity of the 2.5D Si-interposer and also affe
 cting PDN Quality. Manual Routing, an existing design methodol...\n\n\nYou
 ngho Seo, Gwonhyuk Kang, Sangwon Lee, Kun Joo, Donghwi Won, Juhwan Lee, Ji
 nwon Kim, Jungyun Choi, and Youngsoo Sohn (Samsung)\n---------------------
 \nCost and Compute-efficient IR Drop hierarchical signoff for Subsystem De
 signs\n\nWith the increasing reliance on Artificial Intelligence (AI) and 
 the growth of the automotive industry, the need for Power Delivery Network
  (PDN) analysis for subsystems that include GPUs, CPUs, DSPs and Modem bec
 omes more pertinent than ever. The traditional PDN simulations are costly 
 and require a...\n\n\nVarun Sharma (Qualcomm), Ayush Sood and Vineela Gede
 la (Ansys), and Arian Fanaian (Qualcomm)\n---------------------\nGuided Ve
 ctorless with Multi vector profiling for Memory PDN convergence\n\nOptimiz
 ing power grids for modern high-performance chips is crucial for both perf
 ormance and reliability, particularly with the increasing complexity of ad
 vanced technology nodes. While denser grids are ideal for managing voltage
  drops, they often necessitate additional routing tracks, creating layo...
 \n\n\nAlina Sebastian and Mohammed Hafiz (Google)\n---------------------\n
 Comprehensive Power Integrity Analysis of a Super Large Scale 2.5DIC with 
 Multi Silicon Bridges Embedded in Organic Interposer\n\nUltra-large-scale 
 2.5DIC designs with multi silicon bridges embedded on organic interposer s
 how excellent application prospects in various fields such as AI, graphics
  processing, etc., but their development and application also face a serie
 s of challenges, and power integrity is one of the key chall...\n\n\nPing 
 Ding, Guohua Zhou, and Shineng Ma (Sanechips Technology Co.,Ltd) and Li Zo
 u and ShuQiang Zhang (Ansys)\n---------------------\nGenerative-AI Technol
 ogy for block and SoC IR closure: Root-Cause and Repair strategies\n\nPowe
 r integrity is a major design challenge at advanced nodes. The designs are
  becoming increasingly large and complex, along with addition of more comp
 uting resources and innovative algorithms to do EM-IR analysis. This resul
 ts in an unmanageable number of IR drop and EM violations that rely on man
 ...\n\n\nJaikishan Gopal, Siki Yang, Shane Gallagher, Sandhya Karanam, Kei
 th Tunstall, Rohit Somwanshi, and Jinal Apte (Analog Devices, Inc. (ADI))\
 n---------------------\nMachine Learning based Dynamic IR hotspot estimati
 on for SoC Designs\n\nThis presentation introduces a machine learning (ML)
  model for rapid and accurate dynamic IR drop estimation in SoC designs. T
 raditional dynamic IR estimation methods are computationally expensive, wi
 th runtime complexity of N², hindering timely design finalization with goo
 d PPA metrics.\nThis work p...\n\n\nPrateek Pendyala, Jingwei Zhang, and T
  Govindaswamy Rahul Sai (Google)\n\nTopics: AI, Back-End Design, Chiplet\n
 \nSession Chair: Badhri Uppiliappan (BAE Systems)
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