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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T141500
DTEND;TZID=America/Los_Angeles:20250623T143000
UID:dac_DAC 2025_sess224_ENGPRES048@linklings.com
SUMMARY:Comprehensive Power Integrity Analysis of a Super Large Scale 2.5D
 IC with Multi Silicon Bridges Embedded in Organic Interposer
DESCRIPTION:Ping Ding, Guohua Zhou, and Shineng Ma (Sanechips Technology C
 o.,Ltd) and Li Zou and ShuQiang Zhang (Ansys)\n\nUltra-large-scale 2.5DIC 
 designs with multi silicon bridges embedded on organic interposer show exc
 ellent application prospects in various fields such as AI, graphics proces
 sing, etc., but their development and application also face a series of ch
 allenges, and power integrity is one of the key challenges, including:\n·H
 igh-density interconnect: Integration of multiple SoC/chip modules and mem
 ories in a compact space results in high transient current fluctuations, p
 lacing extremely high demands on the power delivery network (PDN)\n·Noise 
 suppression: Due to high-frequency operation, special attention needs to b
 e paid to the control of power supply noise, especially AC noise and synch
 ronous switching noise\n·Dynamic load response: Rapidly changing workloads
  require PDN to be able to respond quickly and maintain voltage stability\
 n    Therefore, we need to consider a number of factors and adopt a series
  of measures to ensure stable power supply and minimize noise. Silicon bri
 dge not only help realize high-density interconnects but also provide sign
 ificant advantages in power integrity. \nBy placing more Deep Trench Capac
 itor (DTC) on the silicon bridge in close proximity to the point of load, 
 it helps to respond quickly to transient current changes. Silicon bridges 
 can shorten PDN transfer path, they also allow the use of multiple power g
 round planes, and they extend the power and ground planes directly near ea
 ch functional module, reducing voltage drop to enhance power supply stabil
 ity.  \n    In contrast to the traditional verification of the robustness 
 of PDNs at signoff phase only, we use big data analytics EDA tools to perf
 orm early analysis of the PDN to establish whether the DTC configuration s
 trategy on the silicon bridge is appropriate, whether the multilayer power
  and ground planes are effective, and whether the PDN network is at risk, 
 to predict potential problems early in the design and to adjust the design
  plan in advance. In the mid-design and signoff phases, we can perform pow
 er integrity analysis of the entire super huge 2.5DIC system to ensure tha
 t the PDN design meets the target impedance requirements.\n\nkeywords : 2.
 5DIC, silicon bridge, power integrity\n\nTopics: AI, Back-End Design, Chip
 let\n\nSession Chair: Badhri Uppiliappan (BAE Systems)\n\n
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