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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T133000
DTEND;TZID=America/Los_Angeles:20250623T134500
UID:dac_DAC 2025_sess224_ENGPRES077@linklings.com
SUMMARY:IR Drop-Aware PDN Design Methodology for HBM Proxy Package Si-Inte
 rposer with 3D-IC Platform
DESCRIPTION:Youngho Seo, Gwonhyuk Kang, Sangwon Lee, Kun Joo, Donghwi Won,
  Juhwan Lee, Jinwon Kim, Jungyun Choi, and Youngsoo Sohn (Samsung)\n\nAs t
 he number of AI parameters increases, the need for 2.5D packaging, includi
 ng multi-HBM, becomes more necessary. There are more than 12,000 bumps in 
 a single HBM, increasing the design complexity of the 2.5D Si-interposer a
 nd also affecting PDN Quality. Manual Routing, an existing design methodol
 ogy, is difficult to optimize the design after Multi-Physics analysis due 
 to large PDN design turn around time (TAT). \nIn this paper, we propose a 
 new methodology for optimizing the Si-Interposer PDN design based on IR dr
 op results with 3DIC platform. Firstly, we used the PDN Auto Routing featu
 re to design the PDN. Secondly, we established the flow of analyzing Syste
 m Level IR drop. Lastly, by integrating these two flows into Cadence Integ
 rity 3D-IC Platform, PDN design could be efficiently performed from C4Bump
  assign to C4Bump fix.\nThrough PDN Auto-Routing, PDN design time was redu
 ced to less than 3 hours. Compared to HBM3E, PDN Quality improved by 68% a
 nd also total TAT of PDN Design from C4Bump assign to fix decreased by 53%
 . By analyzing IR drop results in the early design stage, we were able to 
 determine the number of layers, effectively reducing manufacturing TAT and
  cost.\n\nTopics: AI, Back-End Design, Chiplet\n\nSession Chair: Badhri Up
 piliappan (BAE Systems)\n\n
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