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BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T144500
DTEND;TZID=America/Los_Angeles:20250623T150000
UID:dac_DAC 2025_sess224_ENGPRES195@linklings.com
SUMMARY:Cost and Compute-efficient IR Drop hierarchical signoff for Subsys
 tem Designs
DESCRIPTION:Varun Sharma (Qualcomm), Ayush Sood and Vineela Gedela (Ansys)
 , and Arian Fanaian (Qualcomm)\n\nWith the increasing reliance on Artifici
 al Intelligence (AI) and the growth of the automotive industry, the need f
 or Power Delivery Network (PDN) analysis for subsystems that include GPUs,
  CPUs, DSPs and Modem becomes more pertinent than ever. The traditional PD
 N simulations are costly and require a lot of resources, this proves to be
  quite difficult for modern systems that have numerous multiple power doma
 ins and billions of devices. This paper introduces Reduced Order Model (RO
 M) for subsystems which provides same physical and electrical impact as th
 at of detailed model while significantly reducing the node, resistor, and 
 current sink counts. Flat level analysis becomes cheaper and quicker with 
 the ROM, without compromising accuracy. CPU designs simulation suggest tha
 t the ROM-based analysis is far more resource efficient than full flat, an
 d can achieve up to 2.5 times improvements in runtime, memory, and disk sp
 ace usage. Comparing ROM results of Static, Dynamic Vectorless, Package an
 alysis and Grid Resistance checks with full-flat simulations further confi
 rms the efficacy of ROM. Therefore, the methodology enhances the design te
 am productivity, shortens time-to-market, and reduces compute resource cos
 ts.  Further developments hope to broaden the scope of ROM applications to
  Electromigration (EM), Electrostatic Discharge (ESD), and 3DIC/2.5D simul
 ations.\n\nTopics: AI, Back-End Design, Chiplet\n\nSession Chair: Badhri U
 ppiliappan (BAE Systems)\n\n
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