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BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T134500
DTEND;TZID=America/Los_Angeles:20250623T140000
UID:dac_DAC 2025_sess224_ENGPRES213@linklings.com
SUMMARY:Guided Vectorless with Multi vector profiling for Memory PDN conve
 rgence
DESCRIPTION:Alina Sebastian and Mohammed Hafiz (Google)\n\nOptimizing powe
 r grids for modern high-performance chips is crucial for both performance 
 and reliability, particularly with the increasing complexity of advanced t
 echnology nodes. While denser grids are ideal for managing voltage drops, 
 they often necessitate additional routing tracks, creating layout space co
 nstraints and potential timing issues. Memory convergence is particularly 
 critical, given its sensitivity to timing, DRC, and IR. The physical imple
 mentation of modern high-performance designs requires numerous time-consum
 ing iterations involving PDN design, IR/Timing analysis, floorplanning, an
 d placement. Accurate identification of the correct switching scenario is 
 vital to prevent over-designing the power grid specification. Utilizing VC
 D as a reliable source of scenarios for DvD simulations is common, but the
 se simulations can be lengthy (around1ms-100ms), requiring weeks to comple
 te a single iteration. Analyzing VCD for a short duration around the peak 
 power window can be optimistic for memories since the worst memory scenari
 os can be missed. In this study, we developed a method to profile multiple
  long vectors to guide a vectorless engine, allowing us to mimic worst-cas
 e memory scenarios. This approach reduces the pessimism found in regular v
 ectorless analysis (which typically activates memories with a full 100% to
 ggle rate), while offering significant runtime improvements compared to fu
 ll-length VCD-based simulations and ensuring 100% switching coverage\n\nTo
 pics: AI, Back-End Design, Chiplet\n\nSession Chair: Badhri Uppiliappan (B
 AE Systems)\n\n
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