BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024532Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250623T143000
DTEND;TZID=America/Los_Angeles:20250623T144500
UID:dac_DAC 2025_sess224_ENGPRES302@linklings.com
SUMMARY:Generative-AI Technology for block and SoC IR closure: Root-Cause 
 and Repair strategies
DESCRIPTION:Jaikishan Gopal, Siki Yang, Shane Gallagher, Sandhya Karanam, 
 Keith Tunstall, Rohit Somwanshi, and Jinal Apte (Analog Devices, Inc. (ADI
 ))\n\nPower integrity is a major design challenge at advanced nodes. The d
 esigns are becoming increasingly large and complex, along with addition of
  more computing resources and innovative algorithms to do EM-IR analysis. 
 This results in an unmanageable number of IR drop and EM violations that r
 ely on manual fixing and missed PPA opportunities. One of the major bottle
 necks of in-design EM-IR analysis is that it is computationally expensive 
 due to the size and coupled nature of the power network. To overcome these
  issues, this submission demonstrates novel AI-driven methodology that eff
 iciently identifies the root-cause and categorizes implementation of effic
 ient IR repair methods. The state-of-art Generative-AI technology automati
 cally mitigates IR drop issues early in the design cycle, enabling improve
 d productivity for time-to-market. Staggering >95% IR-drop fix rate was ac
 hieved on multiple diverse product line designs (4nm and 5nm nodes) withou
 t compromising on Power, Performance and Area. The adapted methodology can
  be further used on System level designs and perform multi-corner, multi-s
 cenario analysis which makes it compatible for all types of designs.\n\nAc
 ronyms: EM: Electromigration, IR: Current x Resistance(Voltage), AI: Artif
 icial Intelligence, PPA: Power Performance Area\n\nTopics: AI, Back-End De
 sign, Chiplet\n\nSession Chair: Badhri Uppiliappan (BAE Systems)\n\n
END:VEVENT
END:VCALENDAR