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BEGIN:VEVENT
DTSTAMP:20260402T024508Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T133000
DTEND;TZID=America/Los_Angeles:20250624T150000
UID:dac_DAC 2025_sess225@linklings.com
SUMMARY:Arrival Pathways for Crossing the Chip-n-Package Routes
DESCRIPTION:Learn the routing strategies to cross the maze of chip to pack
 aged parts delivery - keeping the clocks aligned to finding ways around cr
 owded area or feeding throughs that cut the walls. Get Set and GO!\n\nDete
 rministic On Chip Variation Modeling of Clock Mesh\n\nClock mesh are prefe
 rable clock distribution methods for high frequency clocks because of lowe
 r clock latency/skew and on chip variation tolerance. Static timing analys
 is can't accurately predict the on-chip variation effect in a clock mesh b
 ecause of the multi-driven nets. In this submission, Silic...\n\n\nTushark
 ant Mishra, pradeep kothari, and Ayan Datta (Western Digital)\n-----------
 ----------\nML based PPA Push using XAI\n\nAs the technology node scales d
 own continuously, the complexity of the chip design has increased. The ele
 ctronic design automation (EDA) tools also need to be flexible to handle t
 he design complexity. \nAdvanced EDA tools offer numerous tunable paramete
 rs that can greatly affect physical design quali...\n\n\nKyoungsun Cho, Mi
 ntae Lee, jungho kim, Sungyoul Seo, Kibum Nam, Bonghyun Lee, and Ki-Ok Kim
  (Samsung)\n---------------------\nEfficient Automation Strategy for Packa
 ge Substrate Routing\n\nThe existing automatic routing tools often produce
  design rule violations and fail to meet the required routing completion r
 ate when dealing with the complex electrical connection and constraints. I
 n this work, an algorithm of determining auxiliary point is introduced to 
 guide the auto-routing tool ...\n\n\nKeng Tuan Chang, Chih Yi Huang, Chen 
 Chao Wang, and Chin Pin Hung (Advanced Semiconductor Engineering, Inc.) an
 d Woei Haur Hung and Ting-Chi Wang (National Tsing Hua University)\n------
 ---------------\nA Novel Feedthrough Insertion Methodology for Hierarchica
 l SOC Designs: Achieving Reduction in Die Area\n\nThe reduction of die siz
 e has been a primary goal in systems-on-chip (SoC) designs. While previous
  approaches focused on reducing congestion of the chip as a whole, there h
 as been little effort to specifically alleviate congestion in the top chan
 nel. In channel-based hierarchical non-IO limited SoC ...\n\n\nRajanikant 
 Sakariya, Subhadeep Aich, Vivek Joshi, and Roger Griesmer (Texas Instrumen
 ts)\n---------------------\nRouting Congestion Mitigation Techniques Targe
 ting Dense Designs\n\nChallenging high performance design schedules with c
 ompetitive PPA targets may lead to congested or unrouteable designs during
  EDA backend process. To address these challenges, we propose multiple nov
 el routing congestion mitigation methods including: (1) finer integration 
 of estimated global routin...\n\n\nnancy Zhou (IBM); Lakshmi Reddy (IBM Re
 search); and Alex Suess, Bijian Chen, and Nathaniel Hieter (IBM)\n--------
 -------------\nDynamic Optimization of Skew Balancing through an Innovativ
 e Correct-by-Construct Path Delay Query Technique\n\nSkew- the timing vari
 ation among signals, can severely impact the performance and functionality
  of complex design systems, if not taken care of appropriately. Traditiona
 l skew minimization techniques often focus on individual signals and consi
 der one signal as reference leading to sub-optimal result...\n\n\nTejas Sa
 lunkhe, Subhadeep Aich, and Abhranil Bose (Texas Instruments)\n\nTopics: A
 I, Back-End Design\n\nSession Chair: Patricia Fong (Marvell Semiconductor)
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