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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T143000
DTEND;TZID=America/Los_Angeles:20250624T144500
UID:dac_DAC 2025_sess225_ENGPRES153@linklings.com
SUMMARY:Deterministic On Chip Variation Modeling of Clock Mesh
DESCRIPTION:Tusharkant Mishra, pradeep kothari, and Ayan Datta (Western Di
 gital)\n\nClock mesh are preferable clock distribution methods for high fr
 equency clocks because of lower clock latency/skew and on chip variation t
 olerance. Static timing analysis can't accurately predict the on-chip vari
 ation effect in a clock mesh because of the multi-driven nets. In this sub
 mission, Silicon proven custom statistical approach (SPICE Montecarlo simu
 lation based) used to accurately calculate the total on-chip variation eff
 ect due to process, voltage, Interconnect and temperature variations acros
 s clock mesh. Total uncertainty calculated through above approach is signi
 ficantly lesser when compared to typical on chip variation   penalty with 
 regular clock tree synthesis approach. The reduced clock uncertainty great
 ly simplifies the timing convergence\n\nTopics: AI, Back-End Design\n\nSes
 sion Chair: Patricia Fong (Marvell Semiconductor)\n\n
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