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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T133000
DTEND;TZID=America/Los_Angeles:20250624T134500
UID:dac_DAC 2025_sess225_ENGPRES311@linklings.com
SUMMARY:A Novel Feedthrough Insertion Methodology for Hierarchical SOC Des
 igns: Achieving Reduction in Die Area
DESCRIPTION:Rajanikant Sakariya, Subhadeep Aich, Vivek Joshi, and Roger Gr
 iesmer (Texas Instruments)\n\nThe reduction of die size has been a primary
  goal in systems-on-chip (SoC) designs. While previous approaches focused 
 on reducing congestion of the chip as a whole, there has been little effor
 t to specifically alleviate congestion in the top channel. In channel-base
 d hierarchical non-IO limited SoC designs, inserting feedthroughs can be a
  crucial step during the floorplan stage to enhance routing resource utili
 zation, alleviate congestion in the top channels, and ultimately save die 
 area. Traditional feedthrough insertion approaches are usually carried out
  manually or managed in a flattened design. However, it is challenging to 
 handle the large number of connections at the top, the high dependency on 
 RTL, the integration of new feedthrough ports at the subchip level, and th
 e verification of logical equivalence. We propose a method to address thes
 e challenges by employing a novel feedthrough insertion approach\n\nTopics
 : AI, Back-End Design\n\nSession Chair: Patricia Fong (Marvell Semiconduct
 or)\n\n
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