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BEGIN:VEVENT
DTSTAMP:20260402T024509Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T153000
DTEND;TZID=America/Los_Angeles:20250624T170000
UID:dac_DAC 2025_sess226@linklings.com
SUMMARY:Complete Your Power and Thermal Envelopes with Security and Predic
 tability
DESCRIPTION:Keep your cool while removing heat and not revealing your secr
 ets to performance and security. This season deliver secure designs that d
 on't melt down.\n\nPPA Evaluation of BS-PDN Compared to FS-PDN in the Earl
 y Stage\n\nFS-PDN: (Traditional Power Delivery Network) is used to deliver
  power to silicon mos device, implemented by metal routing and via connect
 ion from bump to device. BS-PDN: (Advanced PDN) moves those PDN to the bac
 kside of silicon substrate and free the routing resource to signal routing
  and provide a ...\n\n\nDean Huang, Andy Wei, Chee How Lim, and Yi-Wei Che
 n (Intel Corporation)\n---------------------\nA Simulation Technique of Th
 ermal Side-Channels from Cryptographic Circuits\n\nThis study investigates
  the potential risks of thermal side-channel leakage in cryptographic circ
 uits. Unlike current-based side-channel attacks, thermal energy presents u
 nique challenges due to its inherent difficulty to confine. Cryptographic 
 operations generate thermal energy as a byproduct, whic...\n\n\nShuhei Yok
 ota, Rikuu Hasegawa, Kazuki Monta, Takaaki Okidono, Takuji Miki, and Makot
 o Nagata (Kobe University)\n---------------------\nMitigation of Functiona
 l Power Dissipation in Parasitic Scan Shift Test Buffers\n\nPower optimiza
 tion is a critical consideration in modern semiconductor design. Recoverin
 g even a fraction of a percent of chip power can significantly impact the 
 chip's cost, feasibility, and overall viability. Buffers to fix hold time 
 violations in scan-test shift paths switch in both functional & ...\n\n\nA
 radhana Kumari and Ankur Bal (STMicroelectronics)\n---------------------\n
 A Hybrid Simulation Technique for High-Speed and Accurate System-Level Sid
 e-Channel Leakage Analysis\n\nEvaluating the tolerance of cryptographic mo
 dules in application-specific ICs (ASICs) against side-channel (SC) attack
 s is typically conducted after silicon manufacturing. However, this post-s
 ilicon approach faces two major challenges: the high cost and time require
 d for ASIC production, and the ina...\n\n\nKazuki Monta (Secafy Co., Ltd.)
 ; Takafumi Oki, Rikuu Hasegawa, Takuya Wadatsumi, Takuji Miki, and Makoto 
 Nagata (Kobe University); and Lang Lin and Norman Chang (Ansys)\n---------
 ------------\n3DIC Thermal-Aware Early Design Optimization\n\n3DIC technol
 ogy nowadays unveil a new avenue for expanding the design capacity and int
 egration density. It is beneficial for faster performance, lower power con
 sumption, miniaturization and lower cost etc. Nevertheless, it comes with 
 new challenges that need to be addressed to make the 3DIC solution...\n\n\
 nChia-Yi Liou, Chih-Hsiang Yang, Kuan-Ting Kuo, Chung-Ching Peng, Venkates
 h Ramamurthy, and Vivek Rajan (Intel Corporation); Narender Akilla, Naresh
  Mummidivarapu, Yashodhara Tarey, and Kumar Subramani (Cadence Design Syst
 ems, Inc.); and Yi Wei Chen (Intel Corporation)\n\nTopics: Back-End Design
 , Chiplet\n\nSession Chair: Amol Joshi (Intel Corporation)
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