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DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T154800
DTEND;TZID=America/Los_Angeles:20250624T160600
UID:dac_DAC 2025_sess226_ENGPRES043@linklings.com
SUMMARY:3DIC Thermal-Aware Early Design Optimization
DESCRIPTION:Chia-Yi Liou, Chih-Hsiang Yang, Kuan-Ting Kuo, Chung-Ching Pen
 g, Venkatesh Ramamurthy, and Vivek Rajan (Intel Corporation); Narender Aki
 lla, Naresh Mummidivarapu, Yashodhara Tarey, and Kumar Subramani (Cadence 
 Design Systems, Inc.); and Yi Wei Chen (Intel Corporation)\n\n3DIC technol
 ogy nowadays unveil a new avenue for expanding the design capacity and int
 egration density. It is beneficial for faster performance, lower power con
 sumption, miniaturization and lower cost etc. Nevertheless, it comes with 
 new challenges that need to be addressed to make the 3DIC solutions succes
 sful. Multiphysics effect is one of the critical challenges, especially fo
 r the thermal dissipation. Various technologies aim to resolve thermal iss
 ues at late design stage, but it could be very time-consuming to converge 
 fatal thermal issues. However, most commercial EDA tools do not support th
 ermal-aware design planning at early design stage. This paper presents a t
 hermal-aware design optimization methodology to resolve thermal issues at 
 early design stage. We proposed to create thermal constraints at early P&R
  stage, and the constraints guide module floorplanning of early design opt
 imization. Verify and fix the thermal constraints violations iteratively a
 t P&R stage without thermal simulation quickly converge the thermal impact
  and module floorplanning. The solution models the thermal impact for earl
 y design optimization and shorten the design cycle between implementation 
 and thermal verification.\n\nTopics: Back-End Design, Chiplet\n\nSession C
 hair: Amol Joshi (Intel Corporation)\n\n
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