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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T160600
DTEND;TZID=America/Los_Angeles:20250624T162400
UID:dac_DAC 2025_sess226_ENGPRES067@linklings.com
SUMMARY:Mitigation of Functional Power Dissipation in Parasitic Scan Shift
  Test Buffers
DESCRIPTION:Aradhana Kumari and Ankur Bal (STMicroelectronics)\n\nPower op
 timization is a critical consideration in modern semiconductor design. Rec
 overing even a fraction of a percent of chip power can significantly impac
 t the chip's cost, feasibility, and overall viability. Buffers to fix hold
  time violations in scan-test shift paths switch in both functional & scan
  operation modes. They stay connected to functional paths and consume powe
 r for lifetime of the chip. The problem becomes worse in multi-clock domai
 n designs. Functional power dissipation in these parasitic scan-test shift
  buffers is a waste. Existing EDA tool's ability to identify these parasit
 ic buffers is leveraged to isolate them in functional mode.\nAn effective 
 technique and automation flow for reducing the dynamic power in contempora
 ry digital designs is presented. Dynamic power saving is achieved without 
 any design or implementation trade-offs. The power recovery is moderate fo
 r large sized, medium frequency designs and higher for smaller high freque
 ncy blocks. All present and future digital circuits can easily adopt the p
 roposed buffer gating technique without any ramifications. The proposed me
 thod is implementation-based techniques which is independent of the chip a
 rchitecture, design size and technology node. The proposed methodology can
  be implemented using existing EDA tools and will not impact the design cy
 cle time.\n\nTopics: Back-End Design, Chiplet\n\nSession Chair: Amol Joshi
  (Intel Corporation)\n\n
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