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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:2012\, Level 2
DTSTART;TZID=America/Los_Angeles:20250624T153000
DTEND;TZID=America/Los_Angeles:20250624T154800
UID:dac_DAC 2025_sess226_ENGPRES176@linklings.com
SUMMARY:A Hybrid Simulation Technique for High-Speed and Accurate System-L
 evel Side-Channel Leakage Analysis
DESCRIPTION:Kazuki Monta (Secafy Co., Ltd.); Takafumi Oki, Rikuu Hasegawa,
  Takuya Wadatsumi, Takuji Miki, and Makoto Nagata (Kobe University); and L
 ang Lin and Norman Chang (Ansys)\n\nEvaluating the tolerance of cryptograp
 hic modules in application-specific ICs (ASICs) against side-channel (SC) 
 attacks is typically conducted after silicon manufacturing. However, this 
 post-silicon approach faces two major challenges: the high cost and time r
 equired for ASIC production, and the inability to pinpoint the sources of 
 unexpected leakage. Simulation-based SC leakage assessments address these 
 issues by enabling evaluations before manufacturing, allowing for immediat
 e design adjustments if required SC leakage tolerance is not met.\nThis pa
 per presents a hybrid simulation method that integrates logic-based and tr
 ansistor-level simulations to overcome the limitations of traditional appr
 oaches. The proposed method offers high accuracy in assessing SC leakage a
 t the cryptographic core level while also estimating the signal-to-noise r
 atio (SNR) across the entire chip. Furthermore, it achieves significantly 
 improved efficiency, generating 1,000 waveforms in 300 hours, which is 282
  times higher efficiency compared to conventional chip-level transistor si
 mulations. This hybrid approach enables rapid and precise SC leakage evalu
 ation, facilitating the development of secure cryptographic ASICs with red
 uced design iteration times and costs.\n\nTopics: Back-End Design, Chiplet
 \n\nSession Chair: Amol Joshi (Intel Corporation)\n\n
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