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DTSTAMP:20260402T024507Z
LOCATION:3010\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T133000
DTEND;TZID=America/Los_Angeles:20250624T150000
UID:dac_DAC 2025_sess254@linklings.com
SUMMARY:On the Limitations of VLSI Structural Manufacturing Test and Futur
 e Directions
DESCRIPTION:Structural testing has been very successful in the VLSI manufa
 cturing process to screen out faulty devices and provide high outgoing pro
 duct quality. However, recent reported data from Google and Meta show that
  faulty chips are escaping the test programs and ending in causing serious
  trouble in field; e.g., Silent Data Corruptions (SDC). Meta recently repo
 rted at International Test Conference 2024 that approximately 78% of in fi
 eld interruptions are attributed to confirmed hardware issues such faulty 
 GPUs, faulty memories, etc. This calls for immediate improvements of used 
 fault models and test patterns at manufacturing test.\n\nThis session addr
 esses the limitations of existing fault models and test generation, and hi
 ghlights further direction for better fault modelling; both for logic and 
 memory. The first talk shows the limitations of (commercial) existing solu
 tions. For example, reliance on the stuck-at fault model persists even tho
 ugh data extracted from the test literature reveals that the percentage of
  defects that exhibit stuck-at fault behaviour has significantly reduced o
 ver the years;  real data measurements will be provided to support stateme
 nt. The second talk shows how increasing random process variations in adva
 nced low-nanometer nodes are introducing timing marginalities that can cau
 se unpredictable failures under adverse operating conditions; such margina
 lities are not considered during test generation for structural manufactur
 ing tests yet. Consequently  it is not detected by currently used industri
 al test programs leading to a significant number of test escapes. The thir
 d talk presents Device-Aware-Test; a new approach that aims at closing the
  gap between fault models and real defects. The approach is demonstrated o
 n an industrial STT-MRAM design.\n\nEnhancing Test Quality by Targeting Ti
 ming Marginalities Due to Process Variations\n\nIncreasing random process 
 variations that impact device parameters in low-nanometer nodes are introd
 ucing unpredictable circuit delays and timing marginalities. These can cau
 se failures under adverse operating conditions in some manufactured instan
 ces of a design. Such faulty circuits often escape m...\n\n\nAdit Singh (A
 uburn University)\n---------------------\nDevice-Aware Test: A Means to At
 tack Unmodeled Defects\n\nThis talk discusses a new test approach called D
 evice-Aware Test (DAT) and applies it to industrial STT-MRAMs designs. DAT
  is a new test approach that goes beyond Cell-Aware Test; it does not assu
 me that a defect in a device can be modeled electrically as a linear resis
 tor (as the state-of-the art a...\n\n\nSaid Hamdioui (Delft University of 
 Technology)\n---------------------\nIncompatible: Test Quality and Fortuit
 ous Detection\n\nRecent publications have reported that the root-cause of 
 SDEs (silent date errors) include defects that escape manufacturing testin
 g. An escaped defect is due to its behavior deviating from what is predict
 ed by the models and metrics utilized for test generation. In order to red
 uce escape, the first...\n\n\nShawn Blanton (Carnegie Mellon University)\n
 \nTopics: EDA\n\nSession Chair: Mehdi B. Tahoori (Karlsruhe Institute of T
 echnology, Faculty of Computer Science)
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