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DTSTAMP:20250625T183018Z
LOCATION:3010\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T133000
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UID:dac_DAC 2025_sess254_SSSN023@linklings.com
SUMMARY:Incompatible: Test Quality and Fortuitous Detection
DESCRIPTION:Shawn Blanton (Carnegie Mellon University)\n\nRecent publicati
 ons have reported that the root-cause of SDEs (silent date errors) include
  defects that escape manufacturing testing. An escaped defect is due to it
 s behavior deviating from what is predicted by the models and metrics util
 ized for test generation. In order to reduce escape, the first step must i
 nvolve understanding how often and in what manner does defect behavior dev
 iate from the models/metrics used for ATPG (automatic test pattern generat
 ion). In this work, we describe and demonstrate a methodology for precisel
 y deriving defect behavior from ATE (automatic test equipment) data collec
 ted from a failing logic circuit. The gap measured between models/metrics 
 and actual defect behavior for a 14nm industrial test chip is so substanti
 al that we conclude that test quality can only be maintained and improved 
 if fortuitous detection is reduced. In other words, understanding and mini
 mizing the deviations between predicted behavior and actual defect behavio
 r are crucial for enhancing test quality in the context of SDEs.\n\nTopics
 : EDA\n\nSession Chair: Mehdi B. Tahoori (Karlsruhe Institute of Technolog
 y, Faculty of Computer Science)\n\n
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