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DTSTART:19700308T020000
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DTSTAMP:20260402T024533Z
LOCATION:3010\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T140000
DTEND;TZID=America/Los_Angeles:20250624T143000
UID:dac_DAC 2025_sess254_SSSN024@linklings.com
SUMMARY:Enhancing Test Quality by Targeting Timing Marginalities Due to Pr
 ocess Variations
DESCRIPTION:Adit Singh (Auburn University)\n\nIncreasing random process va
 riations that impact device parameters in low-nanometer nodes are introduc
 ing unpredictable circuit delays and timing marginalities. These can cause
  failures under adverse operating conditions in some manufactured instance
 s of a design. Such faulty circuits often escape manufacturing tests becau
 se current scan timing tests are generated under the assumption of a singl
 e localized delay fault in the circuit; accumulation of distributed delays
  in a circuit path from variations in multiple gates is not targeted becau
 se path delay tests have not proven practical. While the increasing use of
  at-speed functional tests does detect some variability failures, the cove
 rage of functional tests is known to be limited. This talk examines extrem
 e slow paths from process variations, extracting some unique characteristi
 cs that can be exploited by structural test methods to more effectively sc
 reen out many such failures. The aim is to improve test quality and DPPM l
 evels from postproduction testing.\n\nTopics: EDA\n\nSession Chair: Mehdi 
 B. Tahoori (Karlsruhe Institute of Technology, Faculty of Computer Science
 )\n\n
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